Semiconductor memory device

ABSTRACT

A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of Japanese PatentApplication No. 2021-010074, filed on Jan. 26, 2021, the entire contentsof which are incorporated herein by reference.

BACKGROUND Field

Embodiments herein relate to a semiconductor memory device.

Description of the Related Art

There is known a semiconductor memory device comprising: a substrate; aplurality of conductive layers laminated in a direction intersecting asurface of this substrate; a semiconductor layer facing these pluralityof conductive layers; and a gate insulating layer provided between theconductive layers and the semiconductor layer. The gate insulating layercomprises a memory portion capable of storing data, such as aninsulative charge accumulating film of the likes of silicon nitride(Si₃N₄) or a conductive charge accumulating film of the likes of afloating gate, for example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing a configuration of a memorysystem 10 according to a first embodiment.

FIG. 2 is a schematic block diagram showing a configuration of a memorydie MD according to the first embodiment. FIG. 3 is a schematic circuitdiagram showing a configuration of part of the memory die MD.

FIG. 4 is a schematic circuit diagram showing a configuration of part ofthe memory die MD.

FIG. 5 is a schematic circuit diagram showing a configuration of part ofthe memory die MD.

FIG. 6 is a schematic circuit diagram showing a configuration of part ofthe memory die MD.

FIG. 7 is a schematic circuit diagram showing a configuration of part ofthe memory die MD.

FIG. 8 is a schematic circuit diagram showing a configuration of part ofthe memory die MD.

FIG. 9 is a schematic circuit diagram showing a configuration of part ofthe memory die MD.

FIG. 10 is a schematic plan view of the memory die MD.

FIG. 11 is a schematic cross-sectional view of the memory die MD.

FIG. 12 is a schematic enlarged view of the portion indicated by A inFIG. 10.

FIG. 13 is a schematic plan view in which the structure shown in FIG. 12is shown with part thereof omitted.

FIG. 14 is a schematic plan view in which the structure shown in FIG. 12is shown with part thereof omitted.

FIG. 15 is a schematic plan view in which the structure shown in FIG. 12is shown with part thereof omitted.

FIG. 16 is a schematic plan view in which the structure shown in FIG. 12is shown with part thereof omitted.

FIG. 17 is a schematic enlarged view of the portion indicated by B inFIG. 10.

FIG. 18 is a schematic enlarged view of the portion indicated by C inFIG. 17.

FIG. 19 is a schematic enlarged view of the portion indicated by D inFIG. 11.

FIG. 20 is a schematic enlarged view of FIG. 12.

FIG. 21 is a schematic cross-sectional view in which the structure shownin FIG. 20 has been cut along the line E-E′ and viewed along a directionof the arrows.

FIG. 22A is a schematic histogram for explaining threshold voltage of amemory cell MC storing 3-bit data.

FIG. 22B is a table showing one example of a relationship of thresholdvoltages and stored data of a memory cell MC storing 3-bit data.

FIG. 22C is a table showing another example of a relationship ofthreshold voltages and stored data of a memory cell MC storing 3-bitdata.

FIG. 23 is a schematic cross-sectional view for explaining a readoperation.

FIG. 24 is a timing chart for explaining the read operation.

FIG. 25 is a timing chart for explaining a read operation of asemiconductor memory device according to a second embodiment.

FIG. 26 is a flowchart for explaining a write operation of asemiconductor memory device according to a third embodiment.

FIG. 27 is a schematic cross-sectional view for explaining a programoperation included in the write operation.

FIG. 28 is a schematic cross-sectional view for explaining a verifyoperation included in the write operation.

FIG. 29 is a timing chart for explaining the write operation.

FIG. 30 is a timing chart for explaining the write operation.

FIG. 31 is a timing chart for explaining a write operation of asemiconductor memory device according to a fourth embodiment.

FIG. 32 is a schematic circuit diagram showing a configuration of partof a semiconductor memory device according to a fifth embodiment.

FIG. 33 is a schematic circuit diagram showing a configuration of avariable resistance circuit VR1.

FIG. 34 is a schematic plan view showing a configuration of part of asemiconductor memory device according to a sixth embodiment.

FIG. 35 is a schematic plan view in which FIG. 34 is shown with someconfigurations thereof omitted.

FIG. 36 is a schematic plan view for explaining a modified example ofthe semiconductor memory device according to the sixth embodiment.

FIG. 37 is a schematic plan view for explaining a modified example ofthe semiconductor memory device according to the sixth embodiment.

DETAILED DESCRIPTION

A semiconductor memory device according to an embodiment comprises: asubstrate; a first conductive layer which is separated from thesubstrate in a first direction intersecting a surface of the substrateand extends in a second direction intersecting the first direction; asecond conductive layer which is separated from the substrate and thefirst conductive layer in the first direction and extends in the seconddirection; a third conductive layer which is separated from thesubstrate and the first conductive layer in the first direction, extendsin the second direction, is aligned with the second conductive layer inthe second direction, and is electrically connected to the secondconductive layer; a first semiconductor layer which extends in the firstdirection and faces the first conductive layer and the second conductivelayer; a first charge accumulating portion provided between the firstconductive layer and the first semiconductor layer; a second chargeaccumulating portion provided between the second conductive layer andthe first semiconductor layer; a second semiconductor layer whichextends in the first direction and faces the first conductive layer andthe third conductive layer; a third charge accumulating portion providedbetween the first conductive layer and the second semiconductor layer; afourth charge accumulating portion provided between the third conductivelayer and the second semiconductor layer; a first bit line electricallyconnected to the first semiconductor layer; and a second bit lineelectrically connected to the second semiconductor layer. For example, amagnitude and supply time of one or a plurality of voltages supplied tothe first conductive layer, a magnitude and supply time of one or aplurality of voltages supplied to the first bit line, a stabilizationwaiting time until sense start, and a sense time, in the case of acertain operation being executed on a first memory cell including thefirst charge accumulating portion, are assumed to be first operationparameters. Moreover, a magnitude and supply time of one or a pluralityof voltages supplied to the second conductive layer and the thirdconductive layer, a magnitude and supply time of one or a plurality ofvoltages supplied to the first bit line, a stabilization waiting timeuntil sense start, and a sense time, in the case of the certainoperation being executed on a second memory cell including the secondcharge accumulating portion, are assumed to be second operationparameters. In such a case, at least some of the second operationparameters differ from at least some of the first operation parameters.

Next, semiconductor memory devices according to embodiments will bedescribed in detail with reference to the drawings. Note that thefollowing embodiments are merely examples, and are not shown with theintention of limiting the present invention. Moreover, the followingdrawings are schematic, and, for convenience of description, someconfigurations, and so on, thereof will sometimes be omitted. Moreover,portions that are common to a plurality of embodiments will be assignedwith the same symbols, and descriptions thereof will sometimes beomitted.

Moreover, when a “semiconductor memory device” is referred to in thepresent specification, it will sometimes mean a memory die, and willsometimes mean a memory system including a controller die, of the likesof a memory chip, a memory card, or an SSD (Solid State Drive).Furthermore, it will sometimes mean a configuration including a hostcomputer, of the likes of a smartphone, a tablet terminal, or a personalcomputer. Moreover, when a “control circuit” is referred to in thepresent specification, it will sometimes mean a peripheral circuit ofthe likes of a sequencer provided in a memory die, will sometimes meanthe likes of a controller die or controller chip connected to the memorydie, and will sometimes mean a configuration including both of these.

Moreover, in the present specification, when a first configuration issaid to be “electrically connected” to a second configuration, the firstconfiguration maybe connected to the second configuration directly, orthe first configuration may be connected to the second configuration viathe likes of a wiring, a semiconductor member, or a transistor. Forexample, even when, in the case of three transistors having beenserially connected, the second transistor is in an OFF state, the firsttransistor is still “electrically connected” to the third transistor.

Moreover, in the present specification, when a first configuration issaid to be “connected between” a second configuration and a thirdconfiguration, it will sometimes mean that the first configuration, thesecond configuration, and the third configuration are seriallyconnected, and the second configuration is connected to the thirdconfiguration via the first configuration.

Moreover, in the present specification, when a circuit, or the like, issaid to “electrically conducts” two wirings, or the like, this willsometimes mean, for example, that this circuit, or the like, includes atransistor, or the like, that this transistor, or the like, is providedin a current path between the two wirings, and that this transistor, orthe like, is in an ON state.

Moreover, in the present specification, a certain direction parallel toan upper surface of a substrate will be called an X direction, adirection parallel to the upper surface of the substrate andperpendicular to the X direction will be called a Y direction, and adirection perpendicular to the upper surface of the substrate will becalled a Z direction.

Moreover, in the present specification, sometimes, a direction lyingalong a certain plane will be called a first direction, a directionintersecting the first direction along this certain plane will be calleda second direction, and a direction intersecting this certain plane willbe called a third direction. These first direction, second direction,and third direction may correspond to any of the X direction, the Ydirection, and the Z direction, but need not do so.

Moreover, in the present specification, expressions such as “up” or“down” will be defined with reference to the substrate. For example, anorientation of moving away from the substrate along the above-describedZ direction will be called up, and an orientation of coming closer tothe substrate along the Z direction will be called down. Moreover, whena lower surface or a lower end is referred to for a certainconfiguration, this will be assumed to mean a surface or end portion ona substrate side of this configuration, and when an upper surface or anupper end is referred to for a certain configuration, this will beassumed to mean a surface or end portion on an opposite side to thesubstrate of this configuration. Moreover, a surface intersecting the Xdirection or the Y direction will be called a side surface, and so on.

First Embodiment

[Memory System 10]

FIG. 1 is a schematic block diagram showing a configuration of a memorysystem 10 according to a first embodiment.

The memory system 10 performs read, write, erase, and so on, of userdata, in response to a signal transmitted from a host computer 20. Thememory system 10 is a memory chip, a memory card, an SSD, or anothersystem capable of storing user data, for example. The memory system 10comprises a plurality of memory dies MD and a controller die CD.

The memory die MD stores user data. The memory die MD comprises aplurality of memory blocks BLK. The memory block BLK comprises aplurality of pages PG. The memory block BLK may be an execution unit ofan erase operation. The page PG may be an execution unit of a readoperation and a write operation.

As shown in FIG. 1, the controller die CD is connected to the pluralityof memory dies MD and to the host computer 20. The controller die CDcomprises a logical/physical conversion table 21, an FAT (FileAllocation Table) 22, a number-of-times-of-erase latching unit 23, anECC circuit 24, and an MPU (Micro Processor Unit) 25, for example.

The logical/physical conversion table 21 latches in an associated mannera logical address that has been received from the host computer 20 and aphysical address that has been allocated to a page PG in a memory dieMD. The logical/physical conversion table 21 is realized by the likes ofan unillustrated RAM (Random Access Memory), for example.

The FAT 22 latches FAT information indicating a state of each of thepages PG. As such FAT information, there is information indicating“valid”, “invalid”, “erased”, for example. For example, a page PG whichis “valid” is storing valid data to be read in response to a commandfrom the host computer 20. Moreover, a page PG which is “invalid” isstoring invalid data not to be read in response to a command from thehost computer 20. Moreover, a page PG which is “erased” has undergoneexecution of erase operation, so does not have data stored therein. TheFAT 22 is realized by the likes of an unillustrated RAM, for example.

The number-of-times-of-erase latching unit 23 latches in an associatedmanner a physical address corresponding to a memory block BLK and anumber-of-times that an erase operation has been executed on the memoryblock BLK. The number-of-times-of-erase latching unit 23 is realized bythe likes of an unillustrated RAM, for example.

The ECC circuit 24 detects an error of data that has been read from amemory die MD, and where possible, performs correction of the data.

The MPU 25 refers to the logical/physical conversion table 21, the FAT22, the number-of-times-of-erase latching unit 23, and the ECC circuit24 to perform processing, such as conversion of the logical address andthe physical address, bit error detection/correction, garbage collection(compaction), and wear leveling.

[Circuit Configuration of Memory Die MD]

FIG. 2 is a schematic block diagram showing a configuration of thememory die MD according to the first embodiment. FIGS. 3 to 9 areschematic circuit diagrams showing configurations of parts of the memorydie MD.

Note that in FIG. 2, a plurality of control terminals, and so on, areillustrated. These plurality of control terminals are sometimesindicated as a control terminal corresponding to a high active signal (apositive logic signal). Moreover, the plurality of control terminals aresometimes indicated as a control terminal corresponding to a low activesignal (a negative logic signal). Moreover, the plurality of controlterminals are sometimes indicated as a control terminal corresponding toboth a high active signal and a low active signal. In FIG. 2, a symbolof a control terminal corresponding to a low active signal includes anoverline. In the present specification, a symbol of a control terminalcorresponding to a low active signal includes a slash (“/”). Note thatdescription of FIG. 2 is an exemplification, and that a specific mode isappropriately adjustable. For example, it is possible for some or all ofthe high active signals to be configured as low active signals, or forsome or all of the low active signals to be configured as high activesignals.

As shown in FIG. 2, the memory die MD comprises a memory cell array MCAand a peripheral circuit PC. The peripheral circuit PC comprises avoltage generating circuit VG, a row decoder RD, a sense amplifiermodule SAM, and a sequencer SQC. In addition, the peripheral circuit PCcomprises a cache memory CM, an address register ADR, a command registerCMR, and a status register STR. Moreover, the peripheral circuit PCcomprises an input/output control circuit I/O and a logic circuit CTR.

[Circuit Configuration of Memory Cell Array MCA]

As shown in FIG. 3, the memory cell array MCA comprises theabove-mentioned plurality of memory blocks BLK. These plurality ofmemory blocks BLK each comprise a plurality of string units SU. Theseplurality of string units SU each comprise a plurality of memory stringsMS. One ends of these plurality of memory strings MS are respectivelyconnected to the peripheral circuit PC via bit lines BL. Moreover, theother ends of these plurality of memory strings MS are each connected tothe peripheral circuit PC via a common source line SL.

The memory string MS comprises a drain side select transistor STD, aplurality of memory cells MC (memory transistors), a source side selecttransistor STS, and a source side select transistor STSb. The drain sideselect transistor STD, the plurality of memory cells MC, the source sideselect transistor STS, and the source side select transistor STSb areconnected in series between the bit line BL and the source line SL.Hereafter, the drain side select transistor STD, the source side selecttransistor STS, and the source side select transistor STSb willsometimes simply be called select transistors (STD, STS, STSb).

The memory cell MC is a field effect type transistor. The memory cell MCcomprises a semiconductor layer, a gate insulating film, and a gateelectrode. The semiconductor layer functions as a channel region. Thegate insulating film includes a charge accumulating film. A thresholdvoltage of the memory cell MC changes according to an amount of chargein the charge accumulating film. The memory cell MC stores one bit or aplurality of bits of data. Note that the gate electrodes of theplurality of memory cells MC corresponding to one memory string MS arerespectively connected with word lines WL. These word lines WL arerespectively commonly connected to all of the memory strings MS in onememory block BLK.

The select transistor (STD, STS, STSb) is a field effect typetransistor. The select transistor (STD, STS, STSb) comprises asemiconductor layer, a gate insulating film, and a gate electrode. Thesemiconductor layer functions as a channel region. The gate electrodesof the select transistors (STD, STS, STSb) are respectively connectedwith select gate lines (SGD, SGS, SGSb). One drain side select gate lineSGD is commonly connected to all of the memory strings MS in one stringunit SU. One source side select gate line SGS is commonly connected toall of the memory strings MS in one memory block BLK. One source sideselect gate line SGSb is commonly connected to all of the memory stringsMS in one memory block BLK.

[Circuit Configuration of Voltage Generating Circuit VG]

As shown in FIG. 4, for example, the voltage generating circuit VG (FIG.2) comprises a plurality of voltage generating units vg1-vg3. Thevoltage generating units vg1-vg3 generate voltages of certain magnitudesand output the generated voltages via voltage supply lines L_(VG), in aread operation, a write operation, and an erase operation. For example,the voltage generating unit vg1 outputs a later-mentioned programvoltage V_(PGM) in a write operation. Moreover, the voltage generatingunit vg2 outputs a later-mentioned read pass voltage V_(READ) in a readoperation. Moreover, the voltage generating unit vg2 outputs alater-mentioned write pass voltage V_(PASS) in a write operation.Moreover, the voltage generating unit vg3 outputs a later-mentioned readvoltage in a read operation. Moreover, the voltage generating unit vg3outputs a later-mentioned verify voltage in a write operation. Thevoltage generating units vg1-vg3 may be a booster circuit such as acharge pump circuit, or maybe a step-down circuit such as a regulator,for example. These step-down circuit and booster circuit are eachconnected to a voltage supply line L_(P). The voltage supply line L_(P)is supplied with a power supply voltage V_(CC) or a ground voltageV_(SS) (FIG. 2). These voltage supply lines L_(P) are connected to a padelectrode P, for example. Operation voltages outputted from the voltagegenerating circuit VG are appropriately adjusted according to a controlsignal from the sequencer SQC.

As shown in FIG. 5, for example, a charge pump circuit 32 in the voltagegenerating circuit VG comprises a voltage output circuit 32 a, a voltagedividing circuit 32 b, and a comparator 32 c. The voltage output circuit32 a outputs a voltage V_(OUT) to the voltage supply line L_(VG). Thevoltage dividing circuit 32 b is connected to the voltage supply lineL_(VG). The comparator 32 c outputs a feedback signal FB to the voltageoutput circuit 32 a depending on a magnitude relationship of a voltageV_(OUT)′ outputted from the voltage dividing circuit 32 b and areference voltage V_(REF).

As shown in FIG. 6, the voltage output circuit 32 a comprises aplurality of transistors 32 a 2 a, 32 a 2 b. The plurality oftransistors 32 a 2 a, 32 a 2 b are alternately connected between thevoltage supply line L_(VG) and the voltage supply line L_(P). Thevoltage supply line L_(P) illustrated is supplied with the power supplyvoltage V_(CC). Gate electrodes of the serially connected plurality oftransistors 32 a 2 a, 32 a 2 b are connected to their respective drainelectrodes and capacitors 32 a 3. Moreover, the voltage output circuit32 a comprises an AND circuit 32 a 4, a level shifter 32 a 5 a, and alevel shifter 32 a 5 b. The AND circuit 32 a 4 outputs a logical sum ofa clock signal CLK and the feedback signal FB. The level shifter 32 a 5a outputs an output signal of the AND circuit 32 a 4 in a boosted state.An output terminal of the level shifter 32 a 5 a is connected to thegate electrodes of the transistors 32 a 2 a via the capacitors 32 a 3.The level shifter 32 a 5 b outputs an inverted signal of the outputsignal of the AND circuit 32 a 4 in a boosted state. An output terminalof the level shifter 32 a 5 b is connected to the gate electrodes of thetransistors 32 a 2 b via the capacitors 32 a 3.

When the feedback signal FB is in an “H” state, the clock signal CLK isoutputted from the AND circuit 32 a 4 . As a result, electrons aretransported to the voltage supply line L_(P) from the voltage supplyline L_(VG), and a voltage of the voltage supply line L_(VG) increases.On the other hand, when the feedback signal FB is in an “L” state, theclock signal CLK is not outputted from the AND circuit 32 a 4. Hence,the voltage of the voltage supply line L_(VG) does not increase.

As shown in FIG. 5, the voltage dividing circuit 32 b comprises aresistance element 32 b 2 and a variable resistance element 32 b 4. Theresistance element 32 b 2 is connected between the voltage supply lineL_(VG) and a voltage dividing terminal 32 b 1. The variable resistanceelement 32 b 4 is serially connected between the voltage dividingterminal 32 b 1 and the voltage supply line L_(P). This voltage supplyline L_(P) is supplied with the ground voltage V_(SS). A resistancevalue of the variable resistance element 32 b 4 is adjustable dependingon an operation voltage control signal V_(CTRL). Hence, magnitude of thevoltage V_(OUT)′ of the voltage dividing terminal 32 b 1 is adjustabledepending on the operation voltage control signal V_(CTRL).

As shown in FIG. 7, the variable resistance element 32 b 4 comprises aplurality of current paths 32 b 5. The plurality of current paths 32 b 5are connected in parallel between the voltage dividing terminal 32 b 1and the voltage supply line L_(P). The plurality of current paths 32 b 5each comprise a resistance element 32 b 6 and a transistor 32 b 7 thatare serially connected. Resistance values of the resistance elements 32b 6 provided to each of the current paths 32 b 5 may differ from eachother. Gate electrodes of the transistors 32 b 7 are respectivelyinputted with different bits of the operation voltage control signalV_(CTRL), Moreover, the variable resistance element 32 b 4 may have acurrent path 32 b 8 that does not include the transistor 32 b 7.

As shown in FIG. 5, the comparator 32 c outputs the feedback signal FB.The feedback signal FB attains an “L” state when, for example, thevoltage V_(OUT)′ of the voltage dividing terminal 32 b 1 is larger thanthe reference voltage V_(REF). Moreover, the feedback signal FB attainsan “H” state when, for example, the voltage V_(OUT)′ is smaller than thereference voltage V_(REF).

[Circuit Configuration of Row Decoder RD]

As shown in FIG. 4, for example, the row decoder RD comprises a blockdecoder BLKD, a word line decoder WLD, a driver circuit DRV, and anunillustrated address decoder.

The block decoder BLKD comprises a plurality of block decode units blkd.The plurality of block decode units blkd correspond to the plurality ofmemory blocks BLK in the memory cell array MCA. The block decode unitblkd comprises a plurality of transistors T_(BLK). The plurality oftransistors T_(BLK) correspond to the plurality of word lines WL in thememory block BLK. The transistor T_(BLK) is a field effect type NMOStransistor, for example. A drain electrode of the transistor T_(BLK) isconnected to the word line WL. A source electrode of the transistorT_(BLK) is connected to a wiring CG. The wiring CG is connected to allof the block decode units blkd in the block decoder BLKD. A gateelectrode of the transistor T_(BLK) is connected to a signal lineBLKSEL. A plurality of the signal lines BLKSEL are providedcorrespondingly to all of the block decode units blkd. Moreover, thesignal line BLKSEL is connected to all of the transistors T_(BLK) in theblock decode unit blkd.

In a read operation, a write operation, and so on, for example, onesignal line BLKSEL corresponding to a block address in the addressregister ADR (FIG. 2) attains an “H” state, and other signal linesBLKSEL attain an “L” state. For example, the one signal line BLKSEL issupplied with a certain drive voltage having a positive magnitude, andthe other signal lines BLKSEL are supplied with the ground voltageV_(SS), or the like. As a result, all of the word lines WL in the onememory block BLK corresponding to this block address are electricallyconducted with all of the wirings CG. Moreover, all of the word lines WLin the other memory blocks BLK attain a floating state.

The word line decoder WLD comprises a plurality of word line decodeunits wld. The plurality of word line decode units wld correspond to theplurality of memory cells MC in the memory string MS. In the exampleillustrated, the word line decode unit wld comprises two transistorsT_(WLS), T_(WLU). The transistors T_(WLS), T_(WLU) are field effect typeNMOS transistors, for example. Drain electrodes of the transistorsT_(WLS), T_(WLU) are connected to the wiring CG. A source electrode ofthe transistor T_(WLS) is connected to a wiring CG_(S). A sourceelectrode of the transistor T_(WLU) is connected to a wiring CG_(U). Agate electrode of the transistor T_(WLS) is connected to a signal lineWLSEL_(S). A gate electrode of the transistor T_(WLU) is connected to asignal line WLSEL_(U). A plurality of the signal lines WLSEL_(S) areprovided correspondingly to the transistors T_(WLS) included in all ofthe word line decode units wld. A plurality of the signal linesWLSEL_(U) are provided correspondingly to the transistors T_(WLU)included in all of the word line decode units wld.

In a read operation, a write operation, and so on, for example, thesignal line WLSEL_(S) corresponding to one word line decode unit wldcorresponding to a page address in the address register ADR (FIG. 2)attains an “H” state, and the signal line WLSEL_(U) corresponding tothis signal line WLSEL_(S) attains an “L” state. Moreover, the signallines WLSEL_(S) corresponding to the other word line decode units wldattain an “L” state, and the signal lines WLSEL_(U) corresponding tothese signal lines WLSEL_(S) attain an “H” state. Moreover, the wiringCG_(S) is supplied with a voltage corresponding to a selected word lineWL. Moreover, the wiring CG_(U) is supplied with a voltage correspondingto an unselected word line WL. As a result, the one word line WLcorresponding to the above-described page address is supplied with thevoltage corresponding to the selected word line WL. Moreover, the otherword lines WL are supplied with the voltage corresponding to theunselected word line WL.

The driver circuit DRV comprises six transistors T_(DRV1)-T_(DRV6), forexample. The transistors T_(DRV1)-T_(DRV6) are field effect type NMOStransistors, for example. Drain electrodes of the transistorsT_(DRV1)-T_(DRV4) are connected to the wiring CG_(S). Drain electrodesof the transistors T_(DRV5), T_(DRV6) are connected to the wiringCG_(U). A source electrode of the transistor T_(DRV1) is connected to anoutput terminal of the voltage generating unit vg1, via a voltage supplyline L_(VG1). Source electrodes of the transistors T_(DRV2), T_(DRV5)are connected to an output terminal of the voltage generating unit vg2,via a voltage supply line L_(VG2). A source electrode of the transistorT_(DRV3) is connected to an output terminal of the voltage generatingunit vg3, via a voltage supply line L_(VG3). Source electrodes of thetransistors T_(DRV4), T_(DRV6) are connected to the pad electrode P, viathe voltage supply line L_(P). Gate electrodes of the transistorsT_(DRV1)-T_(DRV6) are respectively connected with signal linesVSEL1-VSEL6.

In a read operation, a write operation, and so on, for example, one of aplurality of the signal lines VSEL1-VSEL4 corresponding to the wiringCG_(S) attains an “H” state, and the others attain an “L” state.Moreover, one of the two signal lines VSEL5, VSEL6 corresponding to thewiring CG_(U) attains an “H” state, and the other attains an “L” state.

The unillustrated address decoder sequentially refers to a row addressRA of the address register ADR (FIG. 2) according to a control signalfrom the sequencer SQC (FIG. 2), for example. The row address RAincludes the above-mentioned block address and page address. The addressdecoder controls voltages of the above-described signal lines BLKSEL,WLSEL_(S), WLSEL_(U) to an “H” state or an “L” state.

Note that in the example of FIG. 4, the row decoder RD has the blockdecode units blkd provided one each to each one of the memory blocksBLK. However, this configuration can be appropriately changed. Forexample, the block decode units blkd may be provided one each to everytwo or more of the memory blocks BLK.

[Circuit Configuration of Sense Amplifier Module SAM]

As shown in FIG. 8, for example, the sense amplifier module SAM (FIG. 2)comprises a plurality of sense amplifier units SAU. The plurality ofsense amplifier units SAU correspond to a plurality of the bit lines BL.The sense amplifier units SAU each comprise a sense amplifier SA, awiring LBUS, and latch circuits SDL, DL0-DLn_(L), (where n_(L) is anatural number). The wiring LBUS is connected with a pre-charge chargetransistor 55 (FIG. 9). The wiring LBUS is connected to a wiring DBUSvia a switch transistor DSW.

As shown in FIG. 9, the sense amplifier SA comprises a sense transistor41. The sense transistor 41 discharges charge of the wiring LBUSdepending on a current flowing in the bit line BL. A source electrode ofthe sense transistor 41 is connected to a voltage supply line suppliedwith the ground voltage V_(SS). A drain electrode of the sensetransistor 41 is connected to the wiring LBUS via a switch transistor42. Agate electrode of the sense transistor 41 is connected to the bitline BL via a sense node SEN, a discharge transistor 43, a node COM, aclamp transistor 44, and a voltage-withstanding transistor 45. Note thatthe sense node SEN is connected to an internal control signal line CLKSAvia a capacitor 48.

Moreover, the sense amplifier SA comprises a voltage transfer circuit.The voltage transfer circuit selectively causes the node COM and thesense node SEN to be electrically conducted with a voltage supply linesupplied with a voltage V_(DD) or a voltage supply line supplied with avoltage V_(SRC), depending on data latched in the latch circuit SDL. Thevoltage transfer circuit comprises a node N1, a charge transistor 46, acharge transistor 49, a charge transistor 47, and a discharge transistor50. The charge transistor 46 is connected between the node N1 and thesense node SEN. The charge transistor 49 is connected between the nodeN1 and the node COM. The charge transistor 47 is connected between thenode N1 and the voltage supply line supplied with the voltage V_(DD).The discharge transistor 50 is connected between the node N1 and thevoltage supply line supplied with the voltage V_(SRC). Note that gateelectrodes of the charge transistor 47 and the discharge transistor 50are commonly connected to anode INV_S of the latch circuit SDL.

Note that the sense transistor 41, the switch transistor 42, thedischarge transistor 43, the clamp transistor 44, the charge transistor46, the charge transistor 49, and the discharge transistor 50 areenhancement type NMOS transistors, for example. The voltage-withstandingtransistor 45 is a depression type NMOS transistor, for example. Thecharge transistor 47 is a PMOS transistor, for example.

Moreover, a gate electrode of the switch transistor 42 is connected to asignal line STB. A gate electrode of the discharge transistor 43 isconnected to a signal line XXL. A gate electrode of the clamp transistor44 is connected to a signal line BLC. Agate electrode of thevoltage-withstanding transistor 45 is connected to a signal line BLS. Agate electrode of the charge transistor 46 is connected to a signal lineHLL. A gate electrode of the charge transistor 49 is connected to asignal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, BLX areconnected to the sequencer SQC.

The latch circuit SDL comprises a node LAT_S, the node INV_S, aninverter 51, an inverter 52, a switch transistor 53, and a switchtransistor 54. The inverter 51 comprises an output terminal connected tothe node LAT_S and an input terminal connected to the node INV_S. Theinverter 52 comprises an input terminal connected to the node LAT_S andan output terminal connected to the node INV_S. The switch transistor 53is provided in a current path between the node LAT_S and the wiringLBUS. The switch transistor 54 is provided in a current path between thenode INV_S and the wiring LBUS. The switch transistors 53, 54 are NMOStransistors, for example. A gate electrode of the switch transistor 53is connected to the sequencer SQC via a signal line STL. A gateelectrode of the switch transistor 54 is connected to the sequencer SQCvia a signal line STI.

The latch circuits DL0-DLn_(L), are configured substantially similarlyto the latch circuit SDL. However, as mentioned above, the node INV_S ofthe latch circuit SDL is electrically conducted with the gate electrodesof the charge transistor 47 and the discharge transistor 50 in the senseamplifier SA. The latch circuits DL0-DLn_(L), differ from the latchcircuit SDL in this respect.

The switch transistor DSW is an NMOS transistor, for example. The switchtransistor DSW is connected between the wiring LBUS and the wiring DBUS.Agate electrode of the switch transistor DSW is connected to thesequencer SQC via a signal line DBS.

Note that as exemplified in FIG. 8, the above-mentioned signal linesSTB, HLL, XXL, BLX, BLC, BLS are each commonly connected to all of thesense amplifier units SAU included in the sense amplifier module SAM.Moreover, the above-mentioned voltage supply line supplied with thevoltage V_(DD) and voltage supply line supplied with the voltage V_(SRC)are each commonly connected to all of the sense amplifier units SAUincluded in the sense amplifier module SAM. Moreover, the signal lineSTI and the signal line STL of the latch circuit SDL are each commonlyconnected to all of the sense amplifier units SAU included in the senseamplifier module SAM. Similarly, signal lines TI0-TIn_(L), TL0-TLn_(L),corresponding to the signal line STI and the signal line STL in thelatch circuits DL0-DLn_(L), are each commonly connected to all of thesense amplifier units SAU included in the sense amplifier module SAM. Onthe other hand, a plurality of the above-mentioned signal lines DBS arerespectively correspondingly provided to all of the sense amplifierunits SAU included in the sense amplifier module SAM.

[Circuit Configuration of Cache Memory CM]

The cache memory CM (FIG. 2) comprises a plurality of latch circuits.The plurality of latch circuits are connected to the latch circuitswithin the sense amplifier module SAM via the wiring DBUS. Data DATincluded in these plurality of latch circuits is sequentiallytransferred to the sense amplifier module SAM or the input/outputcontrol circuit I/O.

Moreover, the cache memory CM is connected with an unillustrated decodecircuit and an unillustrated switch circuit. The decode circuit decodesa column address CA latched in the address register ADR. The switchcircuit causes the latch circuit corresponding to the column address CAto be electrically conducted with a bus DB (FIG. 2), depending on anoutput signal of the decode circuit.

[Circuit Configuration of Sequencer SQC]

The sequencer SQC (FIG. 2) outputs an internal control signal to the rowdecoder RD, the sense amplifier module SAM, and the voltage generatingcircuit VG, according to command data D_(CMD) latched in the commandregister CMR. In addition, the sequencer SQC appropriately outputs tothe status register STR status data D_(ST) indicating a state of thesequencer SQC itself .

Moreover, the sequencer SQC generates a ready/busy signal, and outputsthe ready/busy signal to a terminal RY//BY. In a period when theterminal RY//BY is in an “L” state (a busy period), access to the memorydie MD is basically prohibited. Moreover, in a period when the terminalRY//BY is in an “H” state (a ready period), access to the memory die MDis allowed.

[Circuit Configuration of Input/Output Control Circuit I/O]

The input/output control circuit I/O comprises data signal input/outputterminals DQ0-DQ7, toggle signal input/output terminals DQS, /DQS, aplurality of input circuits, a plurality of output circuits, a shiftregister, and a buffer circuit. The plurality of input circuits, theplurality of output circuits, the shift register, and the buffer circuitare each connected to terminals supplied with a power supply voltageV_(CCQ) and the ground voltage V_(SS).

Data that has been inputted via the data signal input/output terminalsDQ0-DQ7 is outputted to the cache memory CM, the address register ADR,or the command register CMR from the buffer circuit, depending on aninternal control signal from the logic circuit CTR. Moreover, data to beoutputted via the data signal input/output terminals DQ0-DQ7 is inputtedto the buffer circuit from the cache memory CM or the status registerSTR, depending on an internal control signal from the logic circuit CTR.

Each of the plurality of input circuits include a comparator connectedto any of the data signal input/output terminals DQ0-DQ7 or to both ofthe toggle signal input/output terminals DQS, /DQS, for example. Each ofthe plurality of output circuits include an OCD (Off Chip Driver)circuit connected to any of the data signal input/output terminalsDQ0-DQ7 or to either of the toggle signal input/output terminals DQS,/DQS, for example.

[Circuit Configuration of Logic Circuit CTR]

The logic circuit CTR (FIG. 2) receives an external control signal fromthe controller die CD via external control terminals /CEn, CLE, ALE,/WE, /RE, RE, and outputs an internal control signal to the input/outputcontrol circuit I/O depending on this external control signal.

[Structure of Memory Die MD]

FIG. 10 is a schematic plan view of the memory die MD. FIG. 11 is aschematic cross-sectional view of the memory die MD. Note that FIG. 11is a view for explaining a schematic configuration of the memory die MD,and does not show specific numbers, shapes, arrangements, and so on, ofconfigurations. FIG. 12 is a schematic enlarged view of the portionindicated by A in FIG. 10. However, in FIG. 12, some of configurationsof FIG. 10 (a later-mentioned first hookup region R_(HU1)) are omitted.FIGS. 13 to 16 are schematic plan views in which the structure shown inFIG. 12 is shown with parts thereof omitted. FIG. 17 is a schematicenlarged view of the portion indicated by B in FIG. 10. FIG. 18 is aschematic enlarged view of the portion indicated by C in FIG. 17. FIG.19 is a schematic enlarged view of the portion indicated by D in FIG.11. FIG. 20 is a schematic enlarged view of FIG. 12. FIG. 21 is aschematic cross-sectional view in which the structure shown in FIG. 20has been cut along the line E-E′ and viewed along a direction of thearrows.

Note that FIGS. 13 to 16 illustrate conductive layers 110, of aplurality of the conductive layers 110 shown in FIG. 12, that areprovided at a certain height position (conductive layers 200, conductivelayers 210, conductive layers 220, or conductive layers 230). Moreover,in FIGS. 13 to 16, configurations included in the second and fourthmemory blocks BLK counting from a negative side in the Y direction, of aplurality of the memory blocks BLK aligned in the Y direction, areomitted.

As shown in FIG. 10, for example, the memory die MD comprises asemiconductor substrate 100. In the example illustrated, thesemiconductor substrate 100 is provided with four memory cell arrayregions R_(MCA) aligned in the X direction and the Y direction.Moreover, the memory cell array region R_(MCA) comprises: two memoryhole regions R_(MH) aligned in the X direction; two of the first hookupregions R_(HU1) aligned in the X direction between the two memory holeregions R_(MH); and a second hookup region R_(HU2) provided between thetwo first hookup regions R_(HU1).

As shown in FIG. 11, for example, the memory die MD comprises: thesemiconductor substrate 100; a transistor layer L_(TR) provided on thesemiconductor substrate 100; a wiring layer D0 provided above thetransistor layer L_(TR); a wiring layer D1 provided above the wiringlayer D0; a wiring layer D2 provided above the wiring layer D1; a memorycell array layer L_(MCA1) provided above the wiring layer D2; a memorycell array layer L_(MCA2) provided above the memory cell array layerL_(MCA1); a wiring layer M0 provided above the memory cell array layerL_(MCA2); and unillustrated wiring layers provided above the wiringlayer M0.

[Structure of Semiconductor Substrate 100]

The semiconductor substrate 100 is a semiconductor substrate configuredfrom P type silicon (Si) including P type impurities such as boron (B),for example. A surface of the semiconductor substrate 100 is providedwith: N type well regions including N type impurities such as phosphorus(P); P type well regions including P type impurities such as boron (B);semiconductor substrate regions where the N type well regions and the Ptype well regions are not provided; and insulating regions 1001.

[Structure of Transistor Layer L_(TR)]

As shown in FIG. 11, for example, a wiring layer GC is provided on anupper surface of the semiconductor substrate 100, via an unillustratedinsulating layer. The wiring layer GC includes a plurality of electrodesgc that face the surface of the semiconductor substrate 100. Moreover,each of the regions of the semiconductor substrate 100 and the pluralityof electrodes gc included in the wiring layer GC are respectivelyconnected to contacts CS.

The N type well regions, the P type well regions, and the semiconductorsubstrate regions of the semiconductor substrate 100 respectivelyfunction as the likes of channel regions of a plurality of transistorsTr configuring the peripheral circuit PC and as one of electrodes of aplurality of capacitors configuring the peripheral circuit PC.

The plurality of electrodes gc included in the wiring layer GCrespectively function as the likes of gate electrodes of the pluralityof transistors Tr configuring the peripheral circuit PC and as the otherelectrodes of the plurality of capacitors configuring the peripheralcircuit PC.

The contact CS extends in the Z direction, and has its lower endconnected to an upper surface of the semiconductor substrate 100 or anupper surface of the electrode gc. A connecting portion of the contactCS and the semiconductor substrate 100 is provided with an impurityregion including an N type impurity or a P type impurity. The contact CSmay include, for example, a laminated film of a barrier conductive filmof the likes of titanium nitride (TiN) and a metal film of the likes oftungsten (W), or the like.

[Structure of Wiring Layers D0, D1, D2]

As shown in FIG. 11, for example, a plurality of wirings included in thewiring layers D0, D1, D2 are electrically connected to at least one ofconfigurations in the memory cell array MCA and configurations in theperipheral circuit PC.

The wiring layers D0, D1, D2 respectively include pluralities of wiringsd0, d1, d2. These pluralities of wirings d0, d1, d2 may each include,for example, a laminated film of a barrier conductive film of the likesof titanium nitride (TiN) and a metal film of the likes of tungsten (W),or the like.

[Structure in Memory Hole Region R_(MH) of Memory Cell Array LayersL_(MCA1), L_(MCA2)]

As shown in FIG. 12, for example, the memory cell array layers L_(MCA1),L_(MCA2) are provided with a plurality of the memory blocks BLK alignedin the Y direction. As shown in FIG. 17, for example, the memory blockBLK comprises a plurality of the string units SU aligned in the Ydirection. An inter-block insulating layer ST of the likes of siliconoxide (SiO₂) is provided between two memory blocks BLK adjacent in the Ydirection. As shown in FIG. 18, for example, an inter-string unitinsulating layer SHE of the likes of silicon oxide (SiO₂) is providedbetween two string units SU adjacent in the Y direction.

As shown in FIG. 11, for example, the memory block BLK comprises: aplurality of the conductive layers 110 aligned in the Z direction; and aplurality of semiconductor layers 120 extending in the Z direction.Moreover, as shown in FIG. 19, for example, the memory block BLKcomprises a plurality of gate insulating films 130 respectively providedbetween the plurality of conductive layers 110 and the plurality ofsemiconductor layers 120.

The conductive layer 110 is a substantially plate-like conductive layerextending in the X direction. The conductive layer 110 may include alaminated film of a barrier conductive film of the likes of titaniumnitride (TiN) and a metal film of the likes of tungsten (W), or thelike. Moreover, the conductive layer 110 may include the likes ofpolycrystalline silicon including an impurity such as phosphorus (P) orboron (B), for example. An insulating layer 101 (FIG. 19) of the likesof silicon oxide (SiO₂) is provided between the plurality of conductivelayers 110 aligned in the Z direction.

As shown in FIG. 11, for example, a conductive layer 111 is providedbelow the conductive layers 110. The conductive layer 111 may includethe likes of polycrystalline silicon including an impurity such asphosphorus (P) or boron (B), for example. Moreover, an insulating layerof the likes of silicon oxide (SiO₂) is provided between the conductivelayer 111 and the conductive layers 110.

A conductive layer 112 is provided below the conductive layer 111. Theconductive layer 112 may include the likes of polycrystalline siliconincluding an impurity such as phosphorus (P) or boron (B), for example.Moreover, the conductive layer 112 may include a conductive layer of ametal such as tungsten (W), or a conductive layer of tungsten silicide,and so on, or may include another conductive layer, for example.Moreover, an insulating layer of the likes of silicon oxide (SiO₂) isprovided between the conductive layer 112 and the conductive layer 111.

The conductive layer 112 functions as the source line SL (FIG. 3). Theconductive layer 112 is provided in the memory cell array layerL_(MCA1). The conductive layer 112 is commonly provided for all of thememory blocks BLK included in the memory cell array region R_(MCA) (FIG.10), for example.

The conductive layer 111 functions as the source side select gate lineSGSb (FIG. 3) and as the gate electrodes of the plurality of source sideselect transistors STSb (FIG. 3) connected to this source side selectgate line SGSb. The conductive layer 111 is provided in the memory cellarray layer L_(MCA1), and extends in the X direction over the two memoryhole regions R_(MH), the two first hookup regions R_(HU1) providedbetween the two memory hole regions R_(MH), and the second hookup regionR_(HU2) provided between the two first hookup regions R_(HU1), that arealigned in the X direction. The conductive layer 111 is electricallyindependent every memory block BLK.

Moreover, one or a plurality of the conductive layers 110 positioned ina lowermost layer, of the plurality of conductive layers 110 function asthe source side select gate line SGS (FIG. 3) and as the gate electrodesof the plurality of source side select transistors STS (FIG. 3)connected to this source side select gate line SGS. These conductivelayers 110 are provided in the memory cell array layer L_(MCA1), andextend in the X direction over the two memory hole regions R_(MH), thetwo first hookup regions R_(HU1) provided between the two memory holeregions R_(MH), and the second hookup region R_(HU2) provided betweenthe two first hookup regions R_(HU1), that are aligned in the Xdirection. These plurality of conductive layers 110 are electricallyindependent every memory block BLK.

Moreover, a plurality of the conductive layers 110 positioned abovethese lowermost layer-positioned conductive layers 110 function as someof the word lines WL (FIG. 3) and as the gate electrodes of thepluralities of memory cells MC (FIG. 3) connected to these word linesWL. In the description below, such a conductive layer 110 will sometimesbe called the conductive layer 200 (FIG. 13). As exemplified in FIG. 13,for example, these plurality of conductive layers 200 are provided inthe memory cell array layer L_(MCA1), and extend in the X direction overthe two memory hole regions R_(MH), the two first hookup regions R_(HU1)provided between the two memory hole regions R_(MH) (omitted in FIG. 13;refer to FIG. 10), and the second hookup region R_(HU2) provided betweenthe two first hookup regions R_(HU1), that are aligned in the Xdirection. Each of these plurality of conductive layers 200 comprise:two portions 201 provided in the two memory hole regions R_(MH); and aportion 202 connected to both of these two portions 201. The twoportions 201 are electrically connected to each other via the portion202. Moreover, these plurality of conductive layers 200 are electricallyindependent every memory block BLK.

Moreover, a group of pairs of the conductive layers 110 aligned in the Xdirection is laminated in the Z direction above the just-mentionedplurality of word line WL-functioning conductive layers 200. In thedescription below, such a conductive layer 110 will sometimes be calledthe conductive layer 210 (FIG. 14). These groups of a plurality of theconductive layers 210 function as some of the word lines WL (FIG. 3) andas the gate electrodes of the pluralities of memory cells MC (FIG. 3)connected to these word lines WL. These groups of a plurality of theconductive layers 200 are provided in the memory cell array layerL_(MCA1). As exemplified in FIG. 14, for example, these two conductivelayers 210 each extend in the X direction over one or the other of thememory hole regions R_(MH), one or the other of the first hookup regionsR_(HU1) (omitted in FIG. 14; refer to FIG. 10), and part of the secondhookup region R_(HU2). These two conductive layers 210 are electricallyconnected to each other via contacts CC and a wiring m1 a. Moreover,these plurality of conductive layers 210 are electrically independentevery memory block BLK.

Moreover, a plurality of the conductive layers 110 positioned above thejust-mentioned plurality of word line WL-functioning conductive layers210 function as some of the word lines WL (FIG. 3) and as the gateelectrodes of the pluralities of memory cells MC (FIG. 3) connected tothese word lines WL. Note that in the description below, such aconductive layer 110 will sometimes be called the conductive layer 220(FIG. 15). As exemplified in FIG. 15, for example, these plurality ofconductive layers 220 are provided in the memory cell array layerL_(MCA2), and extend in the X direction over the two memory hole regionsR_(MH), the two first hookup regions R_(HU1) provided between the twomemory hole regions R_(MH) (omitted in FIG. 15; refer to FIG. 10), andthe second hookup region R_(HU2) provided between the two first hookupregions R_(HU1), that are aligned in the X direction. These plurality ofconductive layers 220 comprise: two portions 221 provided in the twomemory hole regions R_(MH); and a portion 222 connected to both of thesetwo portions 221. The two portions 221 are electrically connected toeach other via the portion 222. Moreover, these plurality of conductivelayers 220 are electrically independent every memory block BLK.

Moreover, a group of pairs of the conductive layers 110 aligned in the Xdirection is laminated in the Z direction above the just-mentionedplurality of word line WL-functioning conductive layers 220. In thedescription below, such a conductive layer 110 will sometimes be calledthe conductive layer 230 (FIG. 16). These groups of a plurality of theconductive layers 230 function as some of the word lines WL (FIG. 3) andas the gate electrodes of the pluralities of memory cells MC (FIG. 3)connected to these word lines WL. These groups of a plurality of theconductive layers 230 are provided in the memory cell array layerL_(MCA2). As exemplified in FIG. 16, for example, these two conductivelayers 230 each extend in the X direction over one or the other of thememory hole regions R_(MH), one or the other of the first hookup regionsR_(HU1) (omitted in FIG. 16; refer to FIG. 10), and part of the secondhookup region R_(HU2). These two conductive layers 230 are electricallyconnected to each other via contacts CC and a wiring m1 a. Moreover,these plurality of conductive layers 230 are electrically independentevery memory block BLK.

Moreover, one or a plurality of the conductive layers 110 positionedabove the just-mentioned plurality of word line WL-functioningconductive layers 230 are provided in the memory cell array layerL_(MCA2) and function as the drain side select gate line SGD (FIG. 3)and as the gate electrodes of the plurality of drain side selecttransistors STD (FIG. 3) connected to this drain side select gate lineSGD. As exemplified in FIG. 17, for example, these plurality ofconductive layers 110 have a smaller width in the Y direction than theother conductive layers 110. Moreover, as exemplified in FIG. 18, forexample, the inter-string unit insulating layer SHE is provided betweentwo of the conductive layers 110 adjacent in the Y direction. Theseplurality of conductive layers 110 are each electrically independentevery string unit SU.

As shown in FIG. 18, for example, the semiconductor layers 120 arealigned in a certain pattern in the X direction and the Y direction. Thesemiconductor layer 120 functions as the channel regions of theplurality of memory cells MC and the select transistors (STD, STS, STSb)included in one memory string MS (FIG. 3). The semiconductor layer 120is a semiconductor layer of the likes of polycrystalline silicon (Si),for example. The semiconductor layer 120 has a substantially cylindricalshape, and has its central portion provided with an insulating layer 125(FIG. 19) of the likes of silicon oxide.

As shown in FIG. 11, for example, the semiconductor layer 120 comprises:a semiconductor region 120 _(L), included in the memory cell array layerL_(MCA1); and a semiconductor region 120 _(U) included in the memorycell array layer L_(MCA2). A lower end of the semiconductor layer 120 isconnected to the conductive layer 112. An upper end of the semiconductorlayer 120 is connected to the bit line BL via contacts Ch, Vy.

The semiconductor region 120 _(L) is a substantially cylindrical regionextending in the Z direction. Outer peripheral surfaces of thesemiconductor regions 120 _(L) are each surrounded by the plurality ofconductive layers 110 and conductive layer 111 included in the memorycell array layer L_(MCA1), and face these plurality of conductive layers110 and conductive layer 111. Note that a diameter of a lower endportion (for example, a portion positioned below the plurality ofconductive layers 110 and conductive layer 111 included in the memorycell array layer L_(MCA1)) of the semiconductor region 120 _(L) issmaller than a diameter of an upper end portion (for example, a portionpositioned above the plurality of conductive layers 110 included in thememory cell array layer L_(MCA1)) of the semiconductor region 120 _(L).

The semiconductor region 120 _(U) is a substantially cylindrical regionextending in the Z direction. Outer peripheral surfaces of thesemiconductor regions 120 _(U) are each surrounded by the plurality ofconductive layers 110 included in the memory cell array layer L_(MCA2),and face these plurality of conductive layers 110. Note that a diameterof a lower end portion (for example, a portion positioned below theplurality of conductive layers 110 included in the memory cell arraylayer L_(MCA2)) of the semiconductor region 120 _(U) is smaller than adiameter of an upper end portion (for example, a portion positionedabove the plurality of conductive layers 110 included in the memory cellarray layer L_(MCA2)) of the semiconductor region 120 _(U) and thediameter of the upper end portion of the above-described semiconductorregion 120 _(L).

The gate insulating film 130 (FIG. 19) has a substantially cylindricalshape covering an outer peripheral surface of the semiconductor layer120. The gate insulating film 130 comprises a tunnel insulating film131, a charge accumulating film 132, and a block insulating film 133that are laminated between the semiconductor layer 120 and theconductive layers 110. The tunnel insulating film 131 and the blockinsulating film 133 are insulating films of the likes of silicon oxide(SiO₂), for example. The charge accumulating film 132 is a film capableof accumulating charge, of the likes of silicon nitride (Si₃N₄), forexample. The tunnel insulating film 131, the charge accumulating film132, and the block insulating film 133 have substantially cylindricalshapes, and extend in the Z direction along the outer peripheral surfaceof the semiconductor layer 120 excluding a contacting portion of thesemiconductor layer 120 and the conductive layer 112.

Note that FIG. 19 shows an example where the gate insulating film 130comprises the charge accumulating film 132 of the likes of siliconnitride. However, the gate insulating film 130 may comprise floatinggates of the likes of polycrystalline silicon including an N type or Ptype impurity, for example.

[Structure in First Hookup Region R_(HU1) of Memory Cell Array LayersL_(MCA1), L_(MCA2)]

As shown in FIG. 17, the first hookup region R_(HU1) is provided withcontact connection subregions r_(CC1) that are respectively providedcorrespondingly to the memory blocks BLK. Moreover, regionscorresponding to some of the memory blocks BLK are provided with contactconnection regions R_(C4T).

The contact connection subregion r_(CC1) is provided with end portionsin the X direction of a plurality of the conductive layers 110functioning as the drain side select gate lines SGD. In addition, thecontact connection subregion r_(CC1) is provided with a plurality of thecontacts CC aligned in a matrix-like manner looking from the Zdirection. These plurality of contacts CC extend in the Z direction, andhave their lower ends connected to the conductive layers 110. Thecontact CC may include, for example, a laminated film of a barrierconductive film of the likes of titanium nitride (TiN) and a metal filmof the likes of tungsten (W), or the like.

The contact CC closest to the memory hole region R_(MH), of a pluralityof the contacts CC aligned in the X direction is connected to the firstconductive layer 110 counting from above. Moreover, the contact CCsecond closest to the memory hole region R_(MH) is connected to thesecond conductive layer 110 counting from above. Likewise, the contactCC a-th closest to the memory hole region R_(MH) (where a is a naturalnumber) is connected to the a-th conductive layer 110 counting fromabove. These plurality of contacts CC are connected to drain electrodesof the transistors Tr, via a wiring m0, and so on, of the wiring layerM0, and so on, a contact C4, the wirings d0, d1, d2 in the wiring layersD0, D1, D2, and the contact CS.

Moreover, the first hookup region R_(HU1) is provided with supportstructures HR that are provided in a vicinity of the contact CC. Thesupport structure HR extends in the Z direction and has its lower endconnected to the conductive layer 112, for example. The supportstructure HR includes silicon oxide (SiO₂), for example.

The contact connection region R_(C4T) is provided with two insulatinglayers ST_(O) that are aligned in the Y direction between twointer-block insulating layers ST aligned in the Y direction. Moreover, acontact connection subregion r_(C4T) is provided between these twoinsulating layers ST_(O). Moreover, conductive layer connectionsubregion r₁₁₀ are provided between the inter-block insulating layers STand the insulating layers ST_(O). These regions extend in the Xdirection along the inter-block insulating layer ST.

The insulating layer ST_(O) extends in the Z direction and has its lowerend connected to the conductive layer 112 (FIG. 11). The insulatinglayer ST_(O) includes silicon oxide (SiO₂), for example.

As shown in FIG. 11, for example, the contact connection subregionr_(C4T) comprises: a plurality of insulating layers 110A aligned in theZ direction; and a plurality of the contacts C4 extending in the Zdirection.

The insulating layer 110A is a substantially plate-like insulating layerextending in the X direction. The insulating layer 110A may include aninsulating layer of the likes of silicon nitride (SiN). Insulatinglayers of the likes of silicon oxide (SiO₂) are provided between eachtwo of the plurality of insulating layers 110A aligned in the Zdirection.

A plurality of the contacts C4 are aligned in the X direction. Thecontact C4 may include a laminated film of a barrier conductive film ofthe likes of titanium nitride (TiN) and a metal film of the likes oftungsten (W), or the like. As shown in FIG. 11, for example, outerperipheral surfaces of the contacts C4 are each surrounded by theinsulating layers 110A and insulating layers 101, and are connected tothese insulating layers 110A and insulating layers 101. The contact C4extends in the Z direction, has its upper end connected to the wiring m0in the wiring layer M0, and has its lower end connected to the wiring d2in the wiring layer D2.

As shown in FIG. 17, for example, the conductive layer connectionsubregion r₁₁₀ comprises narrow portions 110 _(C4T) of the plurality ofconductive layers 110 aligned in the Z direction.

[Structure in Second Hookup Region R_(HU2) of Memory Cell Array LayersL_(MCA1), L_(MCA2) ]

As shown in FIG. 12, the second hookup region R_(HU2) is provided with aplurality of contact connection subregions r_(CC2) and plurality of theabove-described contact connection regions R_(C4T), correspondingly tothe plurality of memory blocks BLK.

The contact connection subregion r_(CC2) is provided with parts of theplurality of conductive layers 110 functioning as the word lines WL orsource side select gate line SGS. In addition, the contact connectionsubregion r_(CC2) is provided with a plurality of the contacts CCaligned in the X direction looking from the Z direction. As shown inFIG. 21, these plurality of contacts CC are respectively connected tothe conductive layers 110. Moreover, as shown in FIGS. 11 and 20, theseplurality of contacts CC are connected to the drain electrodes of thetransistors Tr, via the wiring m0, and so on, of the wiring layer M0,and so on, the contact C4, the wirings d0, d1, d2 in the wiring layersD0, D1, D2, and the contact CS.

Note that as shown in FIG. 13, the portion 202 of the conductive layer200 comprises a narrow portion 110 _(CC2) which is provided in thecontact connection subregion r_(CC2). Moreover, a region adjacent in theY direction to this narrow portion 110 _(CC2) is provided with anopening 102 _(CC2). The narrow portion 110 _(CC2), along with the narrowportion 110 _(C4T) in the contact connection region R_(C4T), cause thetwo portions 201 adjacent in the X direction to be electricallyconducted. Moreover, the conductive layer 200 is connected with onecontact CC. The opening 102 _(CC2) is provided with a contact CC whichis connected to a conductive layer 110 provided below the conductivelayer 200 exemplified in FIG. 13.

Moreover, as shown in FIG. 14, the narrow portion 110 _(CC2) of the kindexemplified in FIG. 13 is not provided between the two conductive layers210 aligned in the X direction. Moreover, these two conductive layers210 are respectively connected with the contacts CC. Moreover, theopening 102 _(CC2) is provided between these two conductive layers 210.The opening 102 _(CC2) is provided with contacts CC which are connectedto a conductive layer 110 provided below the conductive layer 210exemplified in FIG. 14.

Moreover, as shown in FIG. 15, the portion 222 of the conductive layer220 comprises the narrow portion 110 _(CC2) which is provided in thecontact connection subregion r_(CC2). Moreover, a region adjacent in theY direction to this narrow portion 110 _(CC2) is provided with theopening 102 _(CC2). The narrow portion 110 _(CC2), along with the narrowportion 110 _(C4T) in the contact connection region R_(C4T), cause thetwo portions 221 adjacent in the X direction to be electricallyconducted. Moreover, the conductive layer 220 is connected with onecontact CC. The opening 102 _(CC2) is provided with a contact CC whichis connected to a conductive layer 110 provided below the conductivelayer 220 exemplified in FIG. 15.

Moreover, as shown in FIG. 16, the narrow portion 110 _(CC2) of the kindexemplified in FIG. 15 is not provided between the two conductive layers230 aligned in the X direction. Moreover, these two conductive layers230 are respectively connected with the contacts CC. Moreover, theopening 102 _(CC2) is provided between these two conductive layers 230.The opening 102 _(CC2) is provided with contacts CC which are connectedto a conductive layer 110 provided below the conductive layer 230exemplified in FIG. 16.

[Structure of Wiring Layer M0, and so on]

As shown in FIG. 11, a plurality of wirings included in the wiring layerM0 are electrically connected to at least one of configurations in thememory cell array layers L_(MCA1), L_(MCA2) and configurations in thetransistor layer L_(TR), for example.

The wiring layer M0 includes a plurality of the wirings m0. Theseplurality of wirings m0 may include, for example, a laminated film of abarrier conductive film of the likes of titanium nitride (TiN) and ametal film of the likes of copper (Cu), or the like.

Some of the plurality of wirings m0 function as the bit lines BL (FIG.3). As shown in FIG. 18, for example, the bit lines BL are aligned inthe X direction and extend in the Y direction. Moreover, these pluralityof bit lines BL are respectively connected to one semiconductor layer120 included in each of the string units SU.

Moreover, some of the plurality of wirings m0 function as wirings m0 aexemplified in FIGS. 13 to 16. The wiring m0 a is a wiring provided in acurrent path between the above-mentioned contact CC and contact C4, andextends in the Y direction.

Moreover, as mentioned above, wiring layers are further provided abovethe wiring layer M0. These wiring layers each include a plurality ofwirings. These plurality of wirings may include, for example, alaminated film of a barrier conductive film of the likes of titaniumnitride (TiN) or tantalum nitride (TaN) and a metal film of the likes ofcopper (Cu), or the like.

Some of these plurality of wirings function as wirings m1 a exemplifiedin FIGS. 14 and 16. The wiring m1 a is a wiring provided in a currentpath between the above-mentioned contact CC and contact C4, and extendsin the X direction.

[Threshold Voltage of Memory Cell MC]

Next, threshold voltage of the memory cell MC will be described withreference to FIGS. 22A, 22B, and 22C.

FIG. 22A is a schematic histogram for explaining threshold voltages ofthe memory cells MC storing 3-bit data. The horizontal axis indicatesvoltage of the word line WL, and the vertical axis indicates number ofmemory cells MC. FIG. 22B is a table showing one example of arelationship of threshold voltages and stored data of the memory cellsMC storing 3-bit data. FIG. 22C is a table showing another example of arelationship of threshold voltages and stored data of the memory cell MCstoring 3-bit data.

In the example of FIG. 22A, the threshold voltages of the memory cellsMC are controlled to eight types of states. The threshold voltages ofthe memory cells MC controlled to an Er state are smaller than an eraseverify voltage V_(VFYEr). Moreover, for example, the threshold voltagesof the memory cells MC controlled to an A state is larger than a verifyvoltage V_(VFYA), but smaller than a verify voltage V_(VFYB). Moreover,for example, the threshold voltages of the memory cells MC controlled toa B state is larger than the verify voltage V_(VFYB), but smaller than averify voltage V_(VFYC). Likewise, the threshold voltages of the memorycells MC controlled to C through F states are respectively larger thanverify voltages V_(VFYC) through V_(VFYF), but smaller than verifyvoltages V_(VFYD) through V_(VFYG). Moreover, for example, the thresholdvoltages of the memory cells MC controlled to a G state is larger thanthe verify voltage V_(VFYG), but smaller than a read pass voltageV_(READ).

Moreover, in the example of FIG. 22A, a read voltage V_(CGAR) is setbetween the threshold voltages corresponding to the Er state and thethreshold voltages corresponding to the A state. Moreover, a readvoltage V_(CGBR) is set between the threshold voltages corresponding tothe A state and the threshold voltages corresponding to the B state.Likewise, read voltages V_(CGCR) through V_(CGGR) are respectively setbetween the threshold voltages corresponding to the B state andthreshold voltages corresponding to the C state through thresholdvoltages corresponding to the F state and threshold voltagescorresponding to the G state.

For example, the Er state corresponds to a lowest threshold voltage. Thememory cells MC in the Er state are the memory cells MC in an erasedstate, for example. The memory cells MC in the Er state are assignedwith data “111”, for example.

Moreover, the A state corresponds to a threshold voltage which is higherthan the threshold voltage corresponding to the above-described Erstate. The memory cells MC in the A state are assigned with data “101”,for example.

Moreover, the B state corresponds to a threshold voltage which is higherthan the threshold voltage corresponding to the above-described A state.The memory cells MC in the B state are assigned with data “001”, forexample.

Likewise, the C through G states in the drawings correspond to thresholdvoltages which are higher than the threshold voltages corresponding tothe B through F states . The memory cells MC in these states areassigned with data “011”, “010”, “110”, “100”, “000”, for example.

Note that in the case of assignation of the kind exemplified in FIG.22B, lower bit data is discriminable by the single read voltageV_(CGDR), middle bit data is discriminable by the three read voltagesV_(CGAR), V_(CGCR), V_(CGFR), and upper bit data is discriminable by thethree read voltages V_(CGBR), V_(CGER), V_(CGGR).

Note that the number of bits of data stored in the memory cell MC, thenumber of states, the assignation of data to each of the states, and soon, may be appropriately changed.

For example, in the case of assignation of the kind exemplified in FIG.22C, lower bit data is discriminable by the single read voltageV_(CGDR), middle bit data is discriminable by the two read voltagesV_(CGBR), V_(CGFR), and upper bit data is discriminable by the four readvoltages V_(CGAR), V_(CGCR), V_(CGER), V_(CGGR).

[Read Operation]

Next, a read operation of the semiconductor memory device according tothe present embodiment will be described.

FIG. 23 is a schematic cross-sectional view for explaining the readoperation. FIG. 24 is a timing chart for explaining the read operation.

Note that in the description below, sometimes, the word line WLrepresenting a target of operation will be called a selected word lineWL_(S), and the other word lines WL will be called unselected word linesWL_(U). Moreover, the description below describes an example where aplurality of memory cells MC included in the string unit SU representinga target of operation and connected to the selected word line WL_(S)(hereafter, sometimes called “selected memory cells MC”) undergoexecution of the read operation. Moreover, in the description below, aconfiguration including such a plurality of selected memory cells MCwill sometimes be called a selected page PG.

At timing t101 of the read operation, as shown in FIG. 24, for example,the unselected word lines WL_(U) are supplied with the read pass voltageV_(READ), whereby the unselected memory cells MC are set to an ON state.Moreover, the selected word line WL_(S) is supplied with a read voltageto be used in read (any of the read voltages V_(CGAR)-V_(CGGR) describedwith reference to FIG. 22A) or a voltage larger than the read voltage.Moreover, the select gate lines (SGD, SGS, SGSb) are supplied with avoltage V_(SG). The voltage V_(SG) has a magnitude of a degree at whicha channel of electrons is formed in the channel regions of the selecttransistors (STD, STS, STSb), whereby the select transistors (STD, STS,STSb) attain an ON state.

In a period from timing t101 to timing t102 of the read operation, awaiting time Ta is provided. The waiting time Ta is a waiting time forcharging the selected word line WL_(S), for example.

At timing t102 of the read operation, the selected word line WL_(S) issupplied with the read voltage to be used in read (any of the readvoltages V_(CGAR)-V_(CGGR) described with reference to FIG. 22D). As aresult, as shown in FIG. 23, for example, some of the selected memorycells MC attain an ON state, and the rest of the selected memory cellsMC attain an OFF state.

At timing t103 of the read operation, for example, the bit lines BLundergo charging, and so on. For example, the latch circuit SDL of FIG.9 is latched with “H”, and states of the signal lines STB, XXL, BLC,BLS, HLL, BLX are set to “L, L, H, H, H, H”. As a result, the bit lineBL and the sense node SEN are supplied with the voltage V_(DD), andcharging of these bit line BL and sense node SEN is started. Moreover,for example, the source line SL (FIG. 3) is supplied with a voltageV_(SRC), whereby charging of this source line SL is started. The voltageV_(SRC) has about the same magnitude as the ground voltage V_(SS), forexample. The voltage V_(SRC) may be a voltage which is both slightlylarger than the ground voltage V_(SS) and sufficiently smaller than thevoltage V_(DD), for example.

In a period from timing t103 to timing t104 of the read operation, awaiting time Tb is provided. The waiting time Tb is a waiting time forconverging currents of the bit lines BL, for example.

At timing t104 of the read operation, for example, a voltage of thesignal line BLC is reduced. At this time, the voltage of the signal lineBLC is adjusted to a voltage of a degree at which the clamp transistor44 connected to the signal line BLC (FIG. 9) is maintained unchanged inan ON state. As a result, the voltage of the bit line BL decreases.

In a period from timing t104 to timing t105 of the read operation (FIG.24), a waiting time Tc is provided. The waiting time Tc is a waitingtime for stabilizing the currents of the bit lines BL, for example.Hereafter, the waiting time Tc will sometimes be called a “stabilizationwaiting time”.

At timing t105 of the read operation, the sense amplifier module SAM(FIG. 2) is used to detect an ON state/OFF state of the memory cell MCand acquire data indicating the state of this memory cell MC. Hereafter,such an operation will sometimes by called a sense operation. In thesense operation, for example, states of the signal lines STB, XXL, BLC,BLS, HLL, BLX (FIG. 9) are set to “L, H, H, H, L, L”. As a result,charge of the sense node SEN connected to a selected memory cell MC inan ON state is discharged via the bit line BL, and voltage of this sensenode falls. On the other hand, charge of the sense node SEN connected toa selected memory cell MC in an OFF state is maintained, and voltage ofthis sense node is maintained.

In a period from timing t105 to timing t106 of the read operation (FIG.24), a waiting time Td is provided. The waiting time Td is a waitingtime for detecting the state of the memory cell MC, for example.Hereafter, the waiting time Td will sometimes be called a “sense time”.

At timing t106 of the read operation, the sense operation is ended. Forexample, states of the signal lines STB, XXL, BLC, BLS, HLL, BLX (FIG.9) are set to “L, L, L, L, L, L”. As a result, the sense node SEN iselectrically cut off from the bit line BL. Moreover, supply of currentto the bit line BL ends.

Note that at timing t106 or a certain timing after timing t106 of theread operation, the wiring LBUS is charged by the pre-charge transistor55 (FIG. 9), after which the signal line STB is temporarily set to an“H” state, although illustration of this is omitted. Now, the sensetransistor 41 is in an ON state or an OFF state depending on charge ofthe sense node SEN. Hence, voltage of the wiring LBUS is in an “H” stateor an “L” state depending on the charge of the sense node SEN.Subsequently, data of the wiring LBUS is latched by any of the latchcircuit SDL or latch circuits DL0-DLn_(L).

At timing t107 of the read operation, the selected word line WL_(S), theunselected word lines WL_(U), and the select gate lines (SGD, SGS, SGSb)are supplied with the ground voltage V_(SS).

Note that FIG. 24 describes an example where, in the read operation, thesingle read voltage V_(CGDR) alone is supplied to the selected word lineWL_(S), and the sense operation executed a single time in this state.Such an operation is executed when, for example, data is allocated in aform of the kind shown in FIG. 22B, and lower bit data is discriminated.

When, for example, middle bit data is discriminated, the read voltageV_(CGAR) is supplied to the selected word line WL_(S), and the senseoperation executed a single time in this state. Moreover, the readvoltage V_(CGCR) is supplied to the selected word line WL_(S), and thesense operation executed a single time in this state. Moreover, the readvoltage V_(CGFR) is supplied to the selected word line WL_(S), and thesense operation executed a single time in this state.

When, for example, upper bit data is discriminated, the read voltageV_(CGBR) is supplied to the selected word line WL_(S), and the senseoperation executed a single time in this state. Moreover, the readvoltage V_(CGER) is supplied to the selected word line WL_(S), and thesense operation executed a single time in this state. Moreover, the readvoltage V_(CGGR) is supplied to the selected word line WL_(S), and thesense operation executed a single time in this state.

[Variation of Wiring Resistance in Read Operation]

As described with reference to FIGS. 13 and 15, the conductive layer 200and conductive layer 220 respectively comprise: the two portions 201 andtwo portions 221 provided in the two memory hole regions R_(MH); and theportion 202 and portion 222 connected to both of these two portions 201and two portions 221. Moreover, the two portions 201 and two portions221 are respectively electrically connected to each other via theportion 202 and portion 222.

Moreover, as described with reference to FIGS. 14 and 16, the twoconductive layers 210 aligned in the X direction and two conductivelayers 230 aligned in the X direction are separated in the X direction,and electrically connected to each other via the contacts CC and thewirings m0 a, m1 a.

Now, for convenience of manufacturing steps, the plurality of conductivelayers 110 include a highly heat-resistant material such as tungsten (W)or molybdenum (Mo). On the other hand, the wirings m0 a, m1 a include ahighly conductive material such as copper (Cu). In such a configuration,for example, a wiring resistance between the two portions 201 of theconductive layer 200 and wiring resistance between the two portions 221of the conductive layer 220 are larger than a wiring resistance betweenthe two conductive layers 210 aligned in the X direction and wiringresistance between the two conductive layers 230 aligned in the Xdirection.

Now, if, for example, operation parameters of the read operation are setconsidering the case where the conductive layer 200 or conductive layer220 is the selected word line WL_(S), then sometimes, when theconductive layers 210 or the conductive layers 230 becomes the selectedword line WL_(S), a selected memory cell MC that should be determined tobe in an OFF state is determined to be in an ON state.

[Adjustment of Operation Parameters]

In the first embodiment, when the conductive layer 200 or the conductivelayer 220 is the selected word line WL_(S), operation parameters A areused in the read operation. Moreover, when the conductive layer 210 orthe conductive layer 230 is the selected word line WL_(S), operationparameters B are used in the read operation. At least some of operationparameters B differ from operation parameters A.

Operation parameters A, B include, for example, the waiting times Ta,Tb, Tc, Td described with reference to FIG. 24, and so on.

The waiting time Ta in operation parameters B may be shorter than thewaiting time Ta in operation parameters A. Hence, in the read operationin the case of the conductive layer 210 or conductive layer 230 beingthe selected word line WL_(S), excessive charging of the selected wordline WL_(S) can be suppressed. Note that the waiting time Ta inoperation parameters B maybe the same as the waiting time Ta inoperation parameters A.

The waiting time Tb in operation parameters B may be longer than thewaiting time Tb in operation parameters A. Hence, in the read operationin the case of the conductive layer 210 or conductive layer 230 beingthe selected word line WL_(S), currents of the bit lines BL can besuppressed to a degree that effects of excessive charging of theselected word line WL_(S) are canceled. Note that the waiting time Tb inoperation parameters B may be the same as the waiting time Tb inoperation parameters A.

The waiting time Tc in operation parameters B may be longer than thewaiting time Tc in operation parameters A. Hence, in the read operationin the case of the conductive layer 210 or conductive layer 230 beingthe selected word line WL_(S), cell current can be stabilized to adegree that effects of excessive charging of the selected word lineWL_(S) are canceled. Note that the waiting time Tc in operationparameters B may be the same as the waiting time Tc in operationparameters A.

The waiting time Td (sense time) in operation parameters B may beshorter than the waiting time Td (sense time) in operation parameters A.Hence, in the read operation in the case of the conductive layer 210 orconductive layer 230 being the selected word line WL_(S), an amount ofreduction of charge in the sense node SEN can be suppressed to a degreethat effects of excessive charging of the selected word line WL_(S) arecanceled. Note that the waiting time Td in operation parameters B may bethe same as the waiting time Td in operation parameters A.

Moreover, operation parameters A, B include, for example, the voltagesupplied to the selected word line WL_(S) in the period from timing t101to timing t102. For example, when operation parameters A are used, thisvoltage may be a voltage Va0. Moreover, when operation parameters B areused, this voltage may be a voltage Va1. The voltages Va0, Va1 have amagnitude greater than or equal to that of the read voltage (in theexample of FIG. 24, the read voltage V_(CGDR)). The voltage Va1 may besmaller than the voltage Va0. Hence, in the read operation in the caseof the conductive layer 210 or conductive layer 230 being the selectedword line WL_(S), excessive charging of the selected word line WL_(S)can be suppressed. Note that the voltage Va1 may be the same as thevoltage Va0.

Moreover, operation parameters A, B include, for example, the voltagesupplied to the signal line BLC in the period from timing t103 to timingt104. For example, when operation parameters A are used, this voltagemay be a voltage Vb0. Moreover, when operation parameters B are used,this voltage may be a voltage Vb1. The voltage Vb1 may be larger thanthe voltage Vb0. In this case, a voltage V_(BL1) of the bit lines BL atthe timing t104 corresponding to operation parameters B may be largerthan a voltage V_(BL0) of the bit lines BL at the timing t104corresponding to operation parameters A. Hence, in the read operation inthe case of the conductive layer 210 or conductive layer 230 being theselected word line WL_(S), currents of the bit lines BL can besuppressed to a degree that effects of excessive charging of theselected word line WL_(S) are canceled. Note that the voltage Vb1 may bethe same as the voltage Vb0.

In the present embodiment, operation parameters B in the read operationin the case of the conductive layer 210 or conductive layer 230 beingthe selected word line WL_(S) are adjusted so as to differ fromoperation parameters A in the read operation in the case of theconductive layer 200 or conductive layer 220 being the selected wordline WL_(S). As a result, the read operation and cell characteristics inthese cases are uniformized, and quality of the semiconductor memorydevice improves.

Note that in the case of operation parameters A, B having the waitingtimes Ta made different or magnitudes of the voltages Va0, Va1 madedifferent, there is no need for the waiting time Tc in operationparameters B to be made longer than the waiting time Tc in operationparameters A. Hence, time required for the read operation in the case ofthe conductive layer 210 or conductive layer 230 being the selected wordline WL_(S) can be reduced.

Second Embodiment

Next, a semiconductor memory device according to a second embodimentwill be described with reference to FIG. 25. FIG. 25 is a timing chartfor explaining a read operation of same semiconductor memory device.

In the first embodiment, a method of executing the read operation isexemplified with reference to FIG. 24. However, such a method is merelyan exemplification, and the method of executing the read operation maybe appropriately adjusted.

For example, the semiconductor memory device according to the secondembodiment is basically configured similarly to the semiconductor memorydevice according to the first embodiment. Moreover, the read operationaccording to the second embodiment is basically executed similarly tothe read operation according to the first embodiment.

However, in the read operation according to the second embodiment, attiming t101, the selected word line WL_(S) is supplied with the readpass voltage V_(READ).

Moreover, in the read operation according to the second embodiment, attiming t102, the selected word line WL_(S) is supplied with the readvoltage (in the example of FIG. 25, the read voltage V_(CGDR)) or avoltage less than the read voltage.

Moreover, in the read operation according to the second embodiment, inthe period from timing t102 to timing t103, a waiting time Te isprovided. The waiting time Te is a waiting time for discharging chargeof the selected word line WL_(S), for example.

Moreover, in the read operation according to the second embodiment, attiming t103, the selected word line WL_(S) is supplied with the readvoltage.

Moreover, operation parameters A, B according to the second embodimentinclude, for example, the waiting time Te.

The waiting time Te in operation parameters B may be shorter than thewaiting time Te in operation parameters A. Hence, in the read operationin the case of the conductive layer 210 or conductive layer 230 beingthe selected word line WL_(S), excessive discharging of the selectedword line WL_(S) can be suppressed. Note that when a parameter otherthan the waiting time Te is made different between operation parametersA, B, the waiting time Te in operation parameters B may be the same asthe waiting time Te in operation parameters A.

Moreover, operation parameters A, B according to the second embodimentinclude, for example, the voltage supplied to the selected word lineWL_(S) in the period from timing t102 to timing t103. For example, whenoperation parameters A are used, this voltage may be a voltage Ve0.Moreover, when operation parameters B are used, this voltage may be avoltage Ve1. The voltages Ve0, Ve1 have a magnitude less than or equalto that of the read voltage (in the example of FIG. 25, the read voltageV_(CGDR)). The voltage Ve1 may be larger than the voltage Ve0. Hence, inthe read operation in the case of the conductive layer 210 or conductivelayer 230 being the selected word line WL_(S), excessive discharging ofthe selected word line WL_(S) can be suppressed. Note that the voltageVe1 may be the same as the voltage Ve0.

Third Embodiment

Next, a semiconductor memory device according to a third embodiment willbe described with reference to FIGS. 26 to 30.

The first embodiment and the second embodiment describe examples whereoperation parameters used in read operations are adjusted. However, suchaspects are merely exemplifications, and the operation to undergoadjustment of operation parameters used therein, is appropriatelyadjustable.

For example, the semiconductor memory device according to the thirdembodiment is basically configured similarly to the semiconductor memorydevice according to the first embodiment or the second embodiment.However, in the semiconductor memory device according to the thirdembodiment, operation parameters used in a write operation are adjusted.Note that during the read operation of the semiconductor memory deviceaccording to the third embodiment, operation parameters may be adjustedin a similar form to in the first embodiment or the second embodiment,but need not be so adjusted.

[Write Operation]

Next, the write operation of the semiconductor memory device accordingto the present embodiment will be described.

FIG. 26 is a flowchart for explaining the write operation. FIG. 27 is aschematic cross-sectional view for explaining a program operationincluded in the write operation. FIG. 28 is a schematic cross-sectionalview for explaining a verify operation included in the write operation.FIGS. 29 and 30 are timing charts for explaining the write operation.

In step S101, as shown in FIG. 26, for example, a loop count n_(W) isset to 1. The loop count n_(W) is a variable indicating thenumber-of-times of a write loop. Moreover, the latch circuitsDL0-DLn_(L), of the sense amplifier unit SAU (FIG. 9) are latched withuser data to be written to the memory cells MC, for example.

In step S102, the program operation is executed. The program operationis an operation in which the selected word line WL_(S) is supplied witha program voltage to increase the threshold voltage of the memory cellsMC. This operation is executed from timing t121 to timing t125 of FIG.29, for example.

At timing t121 of the program operation, for example, bit lines BL_(W)connected to memory cells MC which are to undergo adjustment of theirthreshold voltages, of the plurality of selected memory cells MC aresupplied with the voltage V_(SRC), and bit lines BL_(P) connected tomemory cells MC which are not to undergo adjustment of their thresholdvoltages, of the plurality of selected memory cells MC are supplied withthe voltage V_(DD). For example, the latch circuit SDL (FIG. 9)corresponding to the bit line BL_(W) is latched with “L”, and the latchcircuit SDL (FIG. 9) corresponding to the bit line BL_(P) is latchedwith “H”. Moreover, states of the signal lines STB, XXL, BLC, BLS, HLL,BLX are set to “L, L, H, H, L, H”. Hereafter, a memory cell MC which isto undergo adjustment of its threshold voltage, of the plurality ofselected memory cells MC will sometimes be called a “write memory cellMC”, and a memory cell MC which is not to undergo adjustment of itsthreshold voltage, of the plurality of selected memory cells MC willsometimes be called a “prohibit memory cell MC”.

At timing t122 of the program operation, the selected word line WL_(S)and the unselected word lines WL_(U) are supplied with a write passvoltage V_(PASS). Moreover, the drain side select gate line SGD issupplied with a voltage V_(SGD). The write pass voltage V_(PASS) has amagnitude greater than or equal to that of the read pass voltageV_(READ) described with reference to FIG. 22A, for example. The voltageV_(SGD) has a magnitude which is smaller than that of the voltage V_(SG)described with reference to FIGS. 23 and 24, and of a degree at whichthe drain side select transistor STD attains an ON state or an OFF statedepending on the voltage of the bit line BL.

At timing t123 of the program operation, the selected word line WL_(S)is supplied with a program voltage V_(PGM). The program voltage V_(PGM)is larger than the write pass voltage V_(PASS).

Now, as shown in FIG. 27, for example, channels of semiconductor layers120 connected to the bit lines BL_(W) are supplied with the voltageV_(SRC). Comparatively large electric fields are generated between suchsemiconductor layers 120 and the selected word line WL_(S). As a result,electrons in the channel of the semiconductor layer 120 tunnel into thecharge accumulating film 132 (FIG. 19) via the tunnel insulating film131 (FIG. 19). Hence, the threshold voltage of the write memory cell MCincreases.

Moreover, channels of semiconductor layers 120 connected to the bitlines BL_(P) are electrically in a floating state, and potentials ofthese channels rise to about the write pass voltage V_(PASS), due tocapacitive coupling with the unselected word lines WL_(U). Electricfields smaller than any of the above-described electric fields aregenerated between such semiconductor layers 120 and the selected wordline WL_(S). As a result, electrons in the semiconductor layer 120 donot tunnel into the charge accumulating film 132 (FIG. 19). Hence, thethreshold voltage of the prohibit memory cell MC does not increase.

In a period from timing t123 to timing t124 of the program operation, awaiting time Tf is provided. The waiting time Tf is a waiting time forincreasing the threshold voltage of the write memory cell MC, forexample.

At timing t124 of the program operation, the selected word line WL_(S)and the unselected word lines WL_(U) are supplied with the write passvoltage V_(PASS).

At timing t125 of the program operation, the selected word line WL_(S),the unselected word lines WL_(U), and the select gate lines (SGD, SGS,SGSb) are supplied with the ground voltage V_(SS).

In step S103 (FIG. 26), the verify operation is performed.

At timing t131 of the verify operation, as shown in FIG. 29, forexample, the selected word line WL_(S) and the unselected word linesWL_(U) are supplied with the read pass voltage V_(READ), whereby all ofthe memory cells MC are set to an ON state. Moreover, the select gatelines (SGD, SGS, SGSb) are supplied with the voltage V_(SG), whereby theselect transistors (STD, STS, STSb) are set to an ON state.

At timing t132 of the verify operation, the selected word line WL_(S) issupplied with a certain verify voltage (any of the verify voltagesV_(VFYA)-V_(VFYG) described with reference to FIG. 22A). As a result, asshown in FIG. 28, for example, some of the selected memory cells MCattain an ON state, and the rest of the selected memory cells MC attainan OFF state.

Moreover, at timing t132, for example, the bit lines BL undergocharging, and so on. At this time, for example, bit lines BL (in theexample of FIG. 29, bit lines BL_(A)) connected to memory cells MCcorresponding to a specific state (in the example of FIG. 29, the Astate) are supplied with the voltage V_(DD), and the other bit lines BLare supplied with the voltage V_(SRC), based on data in the latchcircuits DL0-DLn_(L).

In a period from timing t133 to timing t134 of the verify operation, asshown in FIG. 29, for example, the sense operation is executed. At thistime, the latch circuits DL0-DLn_(L) may be latched with the likes ofdata indicating ON state/OFF state of the memory cells MC.

In a period from timing t135 to timing t137 of the verify operation,processing similar to in a period from timing t132 to timing t134 isperformed for memory cells MC in another state (in the example of FIG.29, the B state). Note that in FIG. 29, a bit line BL connected to amemory cell MC corresponding to the B state is written as bit lineBL_(B).

In a period from timing t138 to timing t140 of the verify operation,processing similar to in the period from timing t132 to timing t134 isperformed for memory cells MC in another state (in the example of FIG.29, the C state). Note that in FIG. 29, a bit line BL connected to amemory cell MC corresponding to the C state is written as bit lineBL_(C).

At timing t141, the selected word line WL_(S) and the unselected wordlines WL_(U) are supplied with the read pass voltage V_(READ), wherebyall of the memory cells MC are set to an ON state. Moreover, the selectgate lines (SGD, SGS, SGSb) are supplied with the voltage V_(SG),whereby the select transistors (STD, STS, STSb) are set to an ON state.

At timing t142 of the verify operation, the selected word line WL_(S),the unselected word lines WL_(U), and the select gate lines (SGD, SGS,SGSb) are supplied with the ground voltage V_(SS).

Subsequently, data latched in the latch circuit SDL is transferred to anunillustrated counter circuit. The counter circuit counts the number ofmemory cells MC whose threshold voltages have reached their targetvalue, or the number of memory cells MC whose threshold voltages havenot reached their target value.

Note that in the example of FIG. 29, there is shown an example wherethree types of verify voltages, namely, the verify voltages V_(VFYA),V_(VFYB), V_(VFYC) are supplied to the selected word line WL_(S) in theverify operation. However, the number of verify voltages supplied to theselected word line WL_(S) in the verify operation may be two types orless, may be four types or more, or, as exemplified in FIG. 30, forexample, may be changed according to the loop count n_(W).

In step S104 (FIG. 26), a result of the verify operation is determined.For example, reference is made to the above-described counter circuit,and in such a case as when the number of memory cells MC whose thresholdvoltages have not reached their target value is a certain number ormore, there is determined to have been a verify FAIL, and operationproceeds to step S105. On the other hand, in such a case as when thenumber of memory cells MC whose threshold voltages have not reachedtheir target value is less than the certain number, there is determinedto have been a verify PASS, and operation proceeds to step S107.

In step S105, it is determined whether the loop count n_(W) has reacheda certain number-of-times N_(W), or not. If N_(W) has not been reached,then operation proceeds to step S106. If N_(W) has been reached, thenoperation proceeds to step S108.

In step S106, the loop count n_(W) is increased by 1, whereuponoperation proceeds to step S102. Moreover, in step S106, a certainvoltage dV is added to the program voltage V_(PGM), for example. Hence,as shown in FIG. 30, for example, the program voltage V_(PGM) increasesalong with increase in the loop count n_(W).

In step S107, status data D_(ST) indicating that the write operationended normally is stored in the status register STR (FIG.2), and thewrite operation is ended. Note that the status data D_(ST) is outputtedto the controller die CD (FIG. 1) in accordance with a status readoperation.

In step S108, status data D_(ST) indicating that the write operation didnot end normally is stored in the status register STR (FIG. 2), and thewrite operation is ended.

[Variation of Wiring Resistance in Write Operation]

As mentioned above, the wiring resistance between the two portions 201(FIG. 13) of the conductive layer 200 and wiring resistance between thetwo portions 221 (FIG. 15) of the conductive layer 220 are larger thanthe wiring resistance between the two conductive layers 210 (FIG. 14)aligned in the X direction and wiring resistance between the twoconductive layers 230 (FIG. 16) aligned in the X direction.

Now, if, for example, operation parameters of the write operation areset considering the case where the conductive layer 200 or conductivelayer 220 is the selected word line WL_(S), then sometimes, when theconductive layers 210 or the conductive layers 230 becomes the selectedword line WL_(S), the threshold voltage of the selected memory cell MCis increasing more than necessary.

[Adjustment of Operation Parameters]

In the semiconductor memory device according to the third embodiment,when the conductive layer 200 or the conductive layer 220 is theselected word line WL_(S), operation parameters C are used in the writeoperation. Moreover, when the conductive layer 210 or the conductivelayer 230 is the selected word line WL_(S), operation parameters D areused in the write operation. At least some of operation parameters Ddiffer from operation parameters C.

Operation parameters C, D include, for example, the waiting time Tfdescribed with reference to FIG. 29.

The waiting time Tf in operation parameters D may be shorter than thewaiting time Tf in operation parameters C. Hence, in the write operationin the case of the conductive layer 210 or conductive layer 230 beingthe selected word line WL_(S), an amount of increase in thresholdvoltage of the selected memory cell MC can be suppressed. Note that thewaiting time Tf in operation parameters D may be the same as the waitingtime Tf in operation parameters C.

Moreover, operation parameters C, D include, for example, an initialvalue of the program voltage V_(PGM) (the program voltage V_(PGM) whenthe loop count n_(W) is 1). As shown in FIG. 30, for example, whenoperation parameters C are used, this voltage may be a voltage Vf0.Moreover, when operation parameters D are used, this voltage may be avoltage Vf1. The voltage Vf1 may be smaller than the voltage Vf0. Hence,in the write operation in the case of the conductive layer 210 orconductive layer 230 being the selected word line WL_(S), an amount ofincrease in threshold voltage of the selected memory cell MC can besuppressed. Note that the voltage Vf1 may be the same as the voltageVf0.

Fourth Embodiment

Next, a semiconductor memory device according to a fourth embodimentwill be described with reference to FIG. 31. FIG. 31 is a timing chartfor explaining a write operation of same semiconductor memory device.

In the third embodiment, a method of executing the write operation isexemplified with reference to FIGS. 26 to 30. However, such a method ismerely an exemplification, and the method of executing the writeoperation may be appropriately adjusted.

For example, the semiconductor memory device according to the fourthembodiment is basically configured similarly to the semiconductor memorydevice according to the third embodiment. However, the write operationaccording to the fourth embodiment differs from the write operationaccording to the third embodiment. The write operation according to thefourth embodiment is basically executed similarly to the write operationaccording to the third embodiment.

However, in the write operation according to the fourth embodiment, attiming t132, the selected word line WL_(S) is supplied with the verifyvoltage to be used first in the verify operation (in the example of FIG.31, the verify voltage V_(VFYA)) or a voltage smaller than thisfirst-to-be-used verify voltage.

Moreover, in the write operation according to the fourth embodiment, ina period from timing t132 to timing t231, a waiting time Te′ isprovided. The waiting time Te′ is a waiting time for discharging chargeof the selected word line WL_(S), for example.

Moreover, in the write operation according to the fourth embodiment, attimings t231, t233, t235, the selected word line WL_(S) is supplied withthe verify voltages (in the example of FIG. 31, the verify voltagesV_(VFYA), V_(VFYB), V_(VFYC)).

Moreover, in the write operation according to the fourth embodiment, ina period from timing t132 to timing t232, a period from timing t135 totiming t234, and a period from timing t138 to timing t236, a waitingtime Tb′ is provided. The waiting time Tb′ is a waiting time forconverging currents of the bit lines BL, for example.

Moreover, in the write operation according to the fourth embodiment, attimings t232, t234, t236, a voltage of the signal line BLC is reduced.At these times, the voltage of the signal line BLC is adjusted to avoltage of a degree at which the clamp transistor 44 connected to thesignal line BLC (FIG. 9) is maintained unchanged in an ON state.

Moreover, in the write operation according to the fourth embodiment, ina period from timing t232 to timing t133, a period from timing t234 totiming t136, and a period from timing t236 to timing t139, a waitingtime Tc′ is provided. The waiting time Tc′ is a waiting time forstabilizing the currents of the bit lines BL, for example. Hereafter,the waiting time Tc′ will sometimes be called a “stabilization waitingtime”.

Moreover, in the write operation according to the fourth embodiment, ina period from timing t133 to timing t134, a period from timing t136 totiming t137, and a period from timing t139 to timing t140, a waitingtime Td′ is provided. The waiting time Td′ is a waiting time fordetecting a state of the memory cell MC, for example. Hereafter, thewaiting time Td′ will sometimes be called a “sense time”.

Moreover, in the write operation according to the fourth embodiment, attimings t135, t138, the selected word line WL_(S) is supplied with theverify voltages to be used next in the verify operation (in the exampleof FIG. 31, the verify voltages V_(VFYB), V_(VFYC)) or voltages largerthan these next-to-be-used verify voltages.

Moreover, in the write operation according to the fourth embodiment, ina period from timing t135 to timing t233 and a period from timing t138to timing t235, a waiting time Ta′ is provided. The waiting time Ta′ isa waiting time for charging the selected word line WL_(S), for example.

Operation parameters C, D according to the fourth embodiment include,for example, the waiting times Ta′, Tb′, Tc′, Td′, Te′.

The waiting time Ta′ in operation parameters D may be shorter than thewaiting time Ta′ in operation parameters C. Hence, in the writeoperation in the case of the conductive layer 210 or conductive layer230 being the selected word line WL_(S), excessive charging of theselected word line WL_(S) can be suppressed. Note that the waiting timeTa′ in operation parameters D may be the same as the waiting time Ta′ inoperation parameters C.

The waiting time Tb′ in operation parameters D may be longer than thewaiting time Tb′ in operation parameters C. Hence, in the writeoperation in the case of the conductive layer 210 or conductive layer230 being the selected word line WL_(S), currents of the bit lines BLcan be suppressed to a degree that effects of excessive charging of theselected word line WL_(S) are canceled. Note that the waiting time Tb′in operation parameters D may be the same as the waiting time Tb′ inoperation parameters C.

The waiting time Tc′ in operation parameters D may be longer than thewaiting time Tc′ in operation parameters C. Hence, in the writeoperation in the case of the conductive layer 210 or conductive layer230 being the selected word line WL_(S), cell current can be stabilizedto a degree that effects of excessive charging of the selected word lineWL_(S) are canceled. Note that the waiting time Tc′ in operationparameters D may be the same as the waiting time Tc′ in operationparameters C.

The waiting time Td′ (sense time) in operation parameters D may beshorter than the waiting time Td′ (sense time) in operation parametersC. Hence, in the write operation in the case of the conductive layer 210or conductive layer 230 being the selected word line WL_(S), an amountof reduction of charge in the sense node SEN can be suppressed to adegree that effects of excessive charging of the selected word lineWL_(S) are canceled. Note that the waiting time Td′ in operationparameters D may be the same as the waiting time Td′ in operationparameters C.

The waiting time Te′ in operation parameters D may be shorter than thewaiting time Te′ in operation parameters C. Hence, in the writeoperation in the case of the conductive layer 210 or conductive layer230 being the selected word line WL_(S), excessive discharging of theselected word line WL_(S) can be suppressed. Note that the waiting timeTe′ in operation parameters D may be the same as the waiting time Te′ inoperation parameters C.

Moreover, operation parameters C, D include, for example, the voltagesupplied to the selected word line WL_(S) in the period from timing t132to timing t231. For example, the voltage when operation parameters D areused may be larger than the voltage when operation parameters C areused. Hence, in the write operation in the case of the conductive layer210 or conductive layer 230 being the selected word line WL_(S),excessive discharging of the selected word line WL_(S) can besuppressed. Note that these voltages may be the same.

Moreover, operation parameters C, D include, for example, the voltagesupplied to the signal line BLC in the period from timing t132 to timingt232. For example, the voltage when operation parameters D are used maybe smaller than the voltage when operation parameters C are used. Hence,in the write operation in the case of the conductive layer 210 orconductive layer 230 being the selected word line WL_(S), currents ofthe bit lines BL can be increased to a degree that effects of excessivedischarging of the selected word line WL_(S) are canceled. Note thatthese voltages may be the same.

Moreover, operation parameters C, D include, for example, the voltagesupplied to the signal line BLC in the period from timing t135 to timingt234 and the period from timing t138 to timing t236. For example, thevoltage when operation parameters D are used may be larger than thevoltage when operation parameters C are used. Hence, in the writeoperation in the case of the conductive layer 210 or conductive layer230 being the selected word line WL_(S), currents of the bit lines BLcan be suppressed to a degree that effects of excessive charging of theselected word line WL_(S) are canceled. Note that these voltages may bethe same.

Moreover, operation parameters C, D include, for example, the voltagesupplied to the selected word line WL_(S) in the period from timing t135to timing t233 and the period from timing t138 to timing t235. Forexample, the voltage when operation parameters D are used may be smallerthan the voltage when operation parameters C are used. Hence, in thewrite operation in the case of the conductive layer 210 or conductivelayer 230 being the selected word line WL_(S), excessive charging of theselected word line WL_(S) can be suppressed. Note that these voltagesmay be the same.

Fifth Embodiment

Next, a semiconductor memory device according to a fifth embodiment willbe described with reference to FIG. 32. FIG. 32 is a schematic circuitdiagram showing a configuration of part of same semiconductor memorydevice.

The semiconductor memory device according to the fifth embodiment isbasically configured similarly to the semiconductor memory deviceaccording to any of the first through fourth embodiments. However, inthe semiconductor memory device according to the fifth embodiment, asexemplified in FIG. 32, for example, a variable resistance circuit VR1is provided in a current path between the voltage generating unit vg1and the transistor T_(DRV1). Moreover, a variable resistance circuit VR3is provided in a current path between the voltage generating unit vg3and the transistor T_(DRV3).

FIG. 33 is a schematic circuit diagram showing a configuration of thevariable resistance circuit VR1. The variable resistance circuit VR1comprises N resistance units U_(VR) connected in series between thevoltage generating unit vg1 and the transistor T_(DRV1). These pluralityof resistance units U_(VR) each comprise a transistor S_(VR) and aresistance element R_(VR) connected in parallel between an inputterminal and an output terminal of the resistance unit U_(VR). Gateelectrodes of the N transistors S_(VR) are respectively connected tosignal lines S₁-S_(N). The N resistance elements R_(VR) may all comprisedifferent resistance values. A resistance value of the variableresistance circuit VR1 is controllable to 2 ^(N) types, according toN-bit data inputted to the signal lines S₁-S_(N), for example. Thevariable resistance circuit VR3 comprises a similar configuration to thevariable resistance circuit VR1, although illustration of this isomitted.

Operation parameters A, B according to the fifth embodiment include, forexample, N-bit data inputted to the variable resistance circuit VR3 in aperiod from timing t101 to timing t102 (FIG. 24), a period from timingt102 to timing t103, and a period from timing t103 to timing t106 of theread operation. For example, the resistance value of the variableresistance circuit VR3 when operation parameters B are used may belarger than the resistance value of the variable resistance circuit VR3when operation parameters A are used. Note that the resistance value ofthe variable resistance circuit VR3 when operation parameters B are usedmay be the same as the resistance value of the variable resistancecircuit VR3 when operation parameters A are used.

Moreover, operation parameters C, D according to the fifth embodimentinclude, for example, N-bit data inputted to the variable resistancecircuit VR1 in a period from timing t123 to timing t124 (FIG. 29) of thewrite operation. For example, the resistance value of the variableresistance circuit VR1 when operation parameters D are used may belarger than the resistance value of the variable resistance circuit VR1when operation parameters C are used. Note that the resistance value ofthe variable resistance circuit VR1 when operation parameters D are usedmay be the same as the resistance value of the variable resistancecircuit VR1 when operation parameters C are used.

Moreover, operation parameters C, D according to the fifth embodimentinclude, for example, N-bit data inputted to the variable resistancecircuit VR3 in a period from timing t131 to timing t132 (FIG. 29), aperiod from timing t132 to timing t231 (FIG. 31), a period from timingt132 to timing t134 (FIG. 31), a period from timing t135 to timing t233(FIG. 31), a period from timing t234 to timing t137 (FIG. 31), a periodfrom timing t138 to timing t235 (FIG. 31) , and a period from timingt236 to timing t140 (FIG. 31) of the write operation. For example, theresistance value of the variable resistance circuit VR3 when operationparameters D are used may be larger than the resistance value of thevariable resistance circuit VR3 when operation parameters C are used.Note that the resistance value of the variable resistance circuit VR3when operation parameters D are used may be the same as the resistancevalue of the variable resistance circuit VR3 when operation parameters Care used.

Note that in the fifth embodiment, any of the operation parametersexemplified in the first through fourth embodiments may be adjusted, butneed not be adjusted.

Moreover, the circuit configurations of the kinds shown in FIGS. 32 and33 are merely exemplifications, and specific configurations areappropriately adjustable. For example, in the example of FIG. 32, eitherof the variable resistance circuits VR1, VR3 may be omitted. Moreover,in the example of FIG. 32, for example, the variable resistance circuitsVR1, VR3 are provided in current paths between the transistors T_(DRV1),T_(DRV3) in the driver circuit DRV and the voltage generating units vg1,vg3. However, it is only required that the variable resistance circuitsbe provided in current paths between the voltage generating units vg1,vg3 and the conductive layers 110. For example, the variable resistancecircuits may be provided in current paths between the transistorsT_(DRV1), T_(DRV3) in the driver circuit DRV and the wiring CG_(S).

Sixth Embodiment

Next, a semiconductor memory device according to a sixth embodiment willbe described with reference to FIGS. 34 and 35. FIG. 34 is a schematicplan view showing a configuration of part of same semiconductor memorydevice. FIG. 35 is a schematic plan view in which FIG. 34 is shown withsome configurations thereof omitted.

In the first through fifth embodiments, effects of variation in wiringresistances are suppressed by adjusting operation parameters in at leastone of the read operation and the write operation. However, such amethod is merely an exemplification, and the method of suppressingvariation in wiring resistance is appropriately adjustable.

For example, the semiconductor memory device according to the sixthembodiment is basically configured similarly to the semiconductor memorydevice according to any of the first through fifth embodiments.

However, as described with reference to FIG. 20, for example, in thesemiconductor memory devices according to the first through fifthembodiments, two conductive layers 210 aligned in the X direction areconnected to one contact C4 via low-resistance wirings m1 a extending inthe X direction, and are connected to the transistor Tr via this onecontact C4. Similarly, two conductive layers 230 aligned in the Xdirection are connected to one contact C4 via low-resistance wirings m1a extending in the X direction, and are connected to the transistor Trvia this one contact C4.

On the other hand, as shown in FIG. 34, for example, in thesemiconductor memory device according to the sixth embodiment, twoconductive layers 230 aligned in the X direction are respectivelyconnected to wirings m0 a extending in the Y direction via contacts CC,and are respectively connected to different contacts C4 via thesewirings m0 a. Moreover, two conductive layers 210 aligned in the Xdirection are respectively connected to wirings m0 a extending in the Ydirection via contacts CC, and are respectively connected to differentcontacts C4 via these wirings m0 a. In addition, as shown in FIG. 35,for example, in the semiconductor memory device according to the sixthembodiment, two conductive layers 230 aligned in the X direction areeach connected to at least any one of wirings d0, d1, d2 extending inthe X direction, via two contacts C4. Moreover, two conductive layers210 aligned in the X direction are each connected to at least any one ofwirings d0, d1, d2 extending in the X direction, via two contacts C4.

Now, as described with reference to FIG. 11, and so on, the wirings d0,d1, d2 include a highly heat-resistant material such as tungsten (W),similarly to the conductive layers 110. Hence, such a configurationenables suppression of a difference between, on the one hand, wiringresistance between the two portions 201 of the conductive layer 200 andwiring resistance between the two portions 221 of the conductive layer220, and on the other hand, wiring resistance between the two conductivelayers 210 aligned in the X direction and wiring resistance between thetwo conductive layers 230 aligned in the X direction.

Note that in the sixth embodiment, any of the operation parametersexemplified in the first through fifth embodiments may be adjusted, butneed not be adjusted.

Moreover, the configurations of the kinds shown in FIGS. 34 and 35 aremerely exemplifications, and specific configurations maybe appropriatelyadjusted. For example, in the example of FIG. 35, the wirings d0, d1, d2for electrically connecting two conductive layers 210 aligned in the Xdirection comprised a substantially linear shape extending in the Xdirection. Similarly, the wirings d0, d1, d2 for electrically connectingtwo conductive layers 230 aligned in the X direction comprised asubstantially linear shape extending in the X direction. However, asshown in FIG. 36, for example, such wirings d0, d1, d2 may comprise aplurality of substantially linear portions dy extending in the Ydirection and aligned in the X direction. Moreover, as shown in FIG. 37,for example, such wirings d0, d1, d2 may comprise a plurality ofsubstantially linear portions dx extending in the X direction andaligned in the Y direction. Such configurations enable wiring resistancebetween two conductive layers 210 aligned in the X direction and wiringresistance between two conductive layers 230 aligned in the X directionto be further increased.

Other Embodiments

That concludes description of the semiconductor memory devices accordingto the first through sixth embodiments. However, the configurations andoperations of the kinds described above are merely exemplifications, andspecific configurations and operations may be appropriately adjusted.

For example, the memory cell arrays MCA according to the first throughsixth embodiments each comprise the two memory cell arrays layersL_(MCA1)/L_(MCA2) aligned in the Z direction, as described withreference to FIG. 11. Moreover, some of the plurality of conductivelayers 110 included in the memory cell array layer L_(MCA1), namely, theconductive layers 200 (FIG. 13) comprise the two portions 201 aligned inthe X direction and the portion 202 connected to these two portions 201,and, above these conductive layers 200, there is provided a group ofpairs of conductive layers 210 (FIG. 14) aligned in the X direction.Moreover, some of the plurality of conductive layers 110 included in thememory cell array layer L_(MCA2), namely, the conductive layers 220(FIG. 15) comprise the two portions 221 aligned in the X direction andthe portion 222 connected to these two portions 221, and, above theseconductive layers 220, there is provided a group of pairs of conductivelayers 230 (FIG. 16) aligned in the X direction.

However, such a configuration is merely an exemplification, and aspecific configuration may be appropriately adjusted.

For example, in the memory cell array MCA according to the first throughsixth embodiments, the memory cell array layer L_(MCA2) may be omitted.In such a case, the memory cell array layer L_(MCA1) may comprise theplurality of conductive layers 110 functioning as the drain side selectgate line SGD, and so on (FIG. 17) .

Moreover, for example, in the memory cell array MCA according to thefirst through sixth embodiments, one or more memory cell array layersmay be provided between the memory cell array layer L_(MCA1) and thememory cell array layer L_(MCA2). Such memory cell array layers may eachinclude a plurality of the conductive layers 110. Moreover, some ofthese plurality of conductive layers 110 may comprise two portionsaligned in the X direction and a portion connected to these twoportions. Moreover, above these some of the conductive layers 110, theremay be provided pairs of the conductive layers 110 aligned in the Xdirection.

Moreover, for example, in the description of the semiconductor memorydevices according to the first through sixth embodiments, aconfiguration having a plurality of NAND-connected memory transistors isexemplified as the configuration of the memory cell array MCA. However,such a configuration is merely an exemplification, and a method ofconnecting the memory transistors maybe appropriately adjusted. Forexample, a configuration having a plurality of NOR-connected memorytransistors may be adopted as the configuration of the memory cell arrayMCA.

Moreover, for example, in the above examples, a configuration in whichan insulative or conductive charge accumulating portion is included inthe gate insulating film is exemplified as the memory transistor.However, such a configuration is merely an exemplification, and theconfiguration included in the gate insulating film of the memorytransistor may be appropriately adjusted. For example, a configurationincluding a ferroelectric substance in the gate insulating film may beadopted as the memory transistor.

Moreover, for example, in the above examples, a configuration having aplurality of memory transistors is exemplified as the configuration ofthe memory cell array MCA. However, such a configuration is merely anexemplification, and a specific configuration is appropriatelyadjustable. For example, a configuration having other than memorytransistors may be adopted as the configuration of the memory cell arrayMCA.

For example, the memory cell array MCA may be a DRAM (Dynamic RandomAccess Memory). The DRAM comprises one or a plurality of capacitors andone or a plurality of transistors. The DRAM undergoescharging/discharging of its capacitor during a write operation and aread operation. A word line is connected to a gate electrode of thetransistor, and a bit line is connected to a source or drain of thetransistor. The configuration of the memory cell array MCA has aplurality of word lines aligned in the Z direction or a plurality of bitlines aligned in the Z direction, for example.

Moreover, for example, the memory cell array MCA may be an SRAM (StaticRandom Access Memory). The SRAM comprises two CMOS inverters. An inputterminal of one is connected to an output terminal of the other, and anoutput terminal of said one is connected to an input terminal of saidother.

Moreover, the memory cell array MCA may be a magnetoresistive memorysuch as an MRAM (Magnetoresistive Random Access Memory) or an STT-MRAM(Spin Transfer Torque MRAM). The MRAM and STT-MRAM include a pair offerromagnetic films and a tunnel insulating film. The pair offerromagnetic films are opposingly disposed. The tunnel insulating filmis provided between the pair of ferromagnetic films. Magnetizationdirections of the ferromagnetic films change in response to the writeoperation.

Moreover, the memory cell array MCA may be a resistance change memorysuch as a ReRAM (Resistive Random Access Memory). The ReRAM includes apair of electrodes and a metal oxide or the like. The metal oxide or thelike is provided between the pair of electrodes. A filament of oxygenvacancies or the like, is formed in the metal oxide or the like, inresponse to a write operation. The pair of electrodes are electricallyconducted with each other or cut off from each other via this filamentof oxygen vacancies or the like.

Moreover, the memory cell array MCA may be a phase change memory such asa PCRAM (Phase Change Random Access Memory) or a PCM (Phase ChangeMemory). The phase change memory may include a chalcogenide film of thelikes of GeSbTe. A crystalline state of the chalcogenide film may changein response to the write operation.

Moreover, in the example of FIG. 36, the wirings d0, d1, d2 forelectrically connecting two conductive layers 210 aligned in the Xdirection and two conductive layers 230 aligned in the X directioncomprise a plurality of substantially linear portions dy extending inthe Y direction and aligned in the X direction. Moreover, in the exampleof FIG. 37, the wirings d0, d1, d2 for electrically connecting twoconductive layers 210 aligned in the X direction and two conductivelayers 230 aligned in the X direction comprise a plurality ofsubstantially linear portions dx extending in the X direction andaligned in the Y direction. However, such configurations are merelyexemplifications, and specific configurations may be appropriatelyadjusted. For example, in the example of FIG. 20, the wirings m0 a, m1 afor electrically connecting two conductive layers 210 aligned in the Xdirection and two conductive layers 230 aligned in the X direction maycomprise a plurality of substantially linear portions extending in the Ydirection and aligned in the X direction. Similarly, in the example ofFIG. 20, the wirings m0 a, m1 a for electrically connecting twoconductive layers 210 aligned in the X direction and two conductivelayers 230 aligned in the X direction may comprise a plurality ofsubstantially linear portions extending in the X direction and alignedin the Y direction.

[Others]

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel methods and systems describedherein may be embodied in a variety of other forms: furthermore, variousomissions, substitutions and changes in the form of the methods andsystems described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

What is claimed is:
 1. A semiconductor memory device comprising: asubstrate; a first conductive layer which is separated from thesubstrate in a first direction intersection a surface of the substrateand extends in a second direction intersecting the first direction; asecond conductive layer which is separated from the substrate and thefirst conductive layer in the first direction and extends in the seconddirection; a third conductive layer which is separated from thesubstrate and the first conductive layer in the first direction, extendsin the second direction, is aligned with the second conductive layer inthe second direction, and is electrically connected to the secondconductive layer; a first semiconductor layer which extends in the firstdirection and faces the first conductive layer and the second conductivelayer; a first charge accumulating portion provided between the firstconductive layer and the first semiconductor layer; a second chargeraccumulating portion provided between the second conductive layer andthe first semiconducter layer; a second semiconductor layer whichextends in the first direction and faces the first conductive layer andthe third conductive layer; a third charge accumulating portion providedbetween the first conductive layer and the second semiconductive layer;a fourth charge accumulating portion provided between the thirdconductive layer and the second semiconductor layer; a first bit lineelectrically connected to the first semiconductor layer; and a secondbit line electrically connected to the second semiconductor layer, whena magnitude and supply time of one or a plurality of voltages suppliedto the first conductive layer, a magnitude and supply time of one or aplurality of voltages supplied to the first bit line, a stabilizationwaiting time until sense start, and a sense time, in the case of acertain operation being executed on a first memory cell including thefirst charge accumulating portion, are assumed to be first operationparameters, and a magnitude and supply time of one or a plurality ofvoltages supplied to the second conductive layer and the thirdconductive layer, a magnitude and supply time of one or a plurality ofvoltages supplied to the first bit line, a stabilization waiting timeuntil sense start, and a sense time, in the case of the certainoperation being executed on a second memory cell including the secondcharge accumulating portion, are assumed to be second operationparameters, at least some of the second operation parameters differingfrom at least some of the first operation parameters.
 2. Thesemiconductor memory device according to claim 1, wherein at least oneof a magnitude and supply time of one or a plurality of voltagessupplied to the second conductive layer and the third conductive layer,in the case of the certain operation being executed on the second memorycell is smaller than at least one of a magnitude and supply time of oneor a plurality of voltages supplied to the first conductive layer, inthe case of the certain operation being executed on the first memorycell.
 3. The semiconductor memory device according to claim 1, whereinat least one of a magnitude and supply time of one or a plurality ofvoltages supplied to the first bit line, in the case of the certainoperation being executed on the second memory cell is larger than atleast one of a magnitude and supply time of one or a plurality ofvoltages supplied to the first bit line, in the case of the certainoperation being executed on the first memory cell.
 4. The semiconductormemory device according to claim 1, wherein a stabilization waiting timeuntil sense start in the case of the certain operation being executed onthe second memory cell is longer than a stabilization waiting time untilsense start in the case of the certain operation being executed on thefirst memory cell.
 5. The semiconductor memory device according to claim1, wherein a sense time in the case of the certain operation beingexecuted on the second memory cell is shorter than a sense time in thecase of the certain operation being executed on the first memory cell.6. The semiconductor memory device according to claim 1, wherein whenthe certain operation is a read operation, and in the case of the readoperation on the first memory cell, at a first timing, the firstconductive layer is supplied with a first voltage, and at a secondtiming later than the first timing, the first conductive layer issupplied with a second voltage which is smaller than the first voltage,and in the case of the read operation on the second memory cell, at athird timing, the second conductive layer and the third conductive layerare supplied with a third voltage, and at a fourth timing later than thethird timing, the second conductive layer and the third conductive layerare supplied with a fourth voltage which is smaller than the thirdvoltage, a time from the third timing to the fourth timing is shorterthan a time from the first timing to the second timing.
 7. Thesemiconductor memory device according to claim 1, wherein when thecertain operation is a read operation, and in the case of the readoperation on the first memory cell, at a first timing, the firstconductive layer is supplied with a first voltage, and at a secondtiming later than the first timing, the first conductive layer issupplied with a second voltage which is smaller than the first voltage,and in the case of the read operation on the second memory cell, at athird timing, the second conductive layer and the third conductive layerare supplied with a third voltage, and at a fourth timing later than thethird timing, the second conductive layer and the third conductive layerare supplied with a fourth voltage which is smaller than or of the samevalue as the third voltage, the third voltage is smaller than the firstvoltage.
 8. The semiconductor memory device according to claim 1,wherein when the certain operation is a read operation, and in the caseof the read operation on the first memory cell, at a first timing, thefirst conductive layer is supplied with a first voltage, at a secondtiming later than the first timing, the first conductive layer issupplied with a second voltage which is smaller than the first voltage,and at a fifth timing between the first timing and the second timing,the first conductive layer is supplied with a fifth voltage which issmaller than the second voltage, and in the case of the read operationon the second memory cell, at a third timing, the second conductivelayer and the third conductive layer are supplied with a third voltage,at a fourth timing later than the third timing, the second conductivelayer and the third conductive layer are supplied with a fourth voltagewhich is smaller than the third voltage, and at a sixth timing betweenthe third timing and the fourth timing, the second conductive layer andthe third conductive layer are supplied with a sixth voltage which issmaller than the fourth voltage, a time from the sixth timing to thefourth timing is shorter than a time from the fifth timing to the secondtiming.
 9. The semiconductor memory device according to claim 1, whereinwhen the certain operation is a read operation, and in the case of theread operation on the first memory cell, at a first timing, the firstconductive layer is supplied with a first voltage, at a second timinglater than the first timing, the first conductive layer is supplied witha second voltage which is smaller than the first voltage, and at a fifthtiming between the first timing and the second timing, the firstconductive layer is supplied with a fifth voltage which is smaller thanthe second voltage, and in the case of the read operation on the secondmemory cell, at a third timing, the second conductive layer and thethird conductive layer are supplied with a third voltage, at a fourthtiming later than the third timing, the second conductive layer and thethird conductive layer are supplied with a fourth voltage which issmaller than the third voltage, and at a sixth timing between the thirdtiming and the fourth timing, the second conductive layer and the thirdconductive layer are supplied with a sixth voltage which is smaller thanor of the same value as the fourth voltage, the sixth voltage is largerthan the fifth voltage.
 10. The semiconductor memory device according toclaim 1, wherein when the certain operation is a read operation, and inthe case of the read operation on the first memory cell, at a seventhtiming, the first bit line is supplied with a seventh voltage, and at aneighth timing later than the seventh timing, the first bit line issupplied with an eighth voltage which is smaller than the seventhvoltage, and in the case of the read operation on the second memorycell, at a ninth timing, the first bit line is supplied with a ninthvoltage, and at a tenth timing later than the ninth timing, the firstbit line is supplied with a tenth voltage which is smaller than theninth voltage, a time from the ninth timing to the tenth timing islonger than a time from the seventh timing to the eighth timing.
 11. Thesemiconductor memory device according to claim 1, wherein when thecertain operation is a read operation, and in the case of the readoperation on the first memory cell, at a seventh timing, the first bitline is supplied with a seventh voltage, and at an eighth timing laterthan the seventh timing, the first bit line is supplied with an eighthvoltage which is smaller than the seventh voltage, and in the case ofthe read operation on the second memory cell, at a ninth timing, thefirst bit line is supplied with a ninth voltage, and at a tenth timinglater than the ninth timing, the first bit line is supplied with a tenthvoltage which is smaller than the ninth voltage, the ninth voltage islarger than the seventh voltage.
 12. The semiconductor memory deviceaccording to claim 1, further comprising: a first transistor, the firsttransistor comprising a gate electrode which is electrically connectedto the first bit line; and a second transistor, the second transistorbeing provided in a current path between the first transistor and thefirst bit line, wherein when the certain operation is a read operation,and in the case of the read operation on the first memory cell, at aseventh timing, a gate electrode of the second transistor is suppliedwith an eleventh voltage, and at an eighth timing later than the seventhtiming, the gate electrode of the second transistor is supplied with atwelfth voltage which is smaller than the eleventh voltage, and in thecase of the read operation on the second memory cell, at a ninth timing,the gate electrode of the second transistor is supplied with athirteenth voltage, and at a tenth timing later than the ninth timing,the gate electrode of the second transistor is supplied with afourteenth voltage which is smaller than the thirteenth voltage, a timefrom the ninth timing to the tenth timing is longer than a time from theseventh timing to the eighth timing.
 13. The semiconductor memory deviceaccording to claim 1, further comprising: a first transistor, the firsttransistor comprising a gate electrode which is electrically connectedto the first bit line; and a second transistor, the second transistorbeing provided in a current path between the first transistor and thefirst bit line, wherein when the certain operation is a read operation,and in the case of the read operation on the first memory cell, at aseventh timing, a gate electrode of the second transistor is suppliedwith an eleventh voltage, and at an eighth timing later than the seventhtiming, the gate electrode of the second transistor is supplied with atwelfth voltage which is smaller than the eleventh voltage, and in thecase of the read operation on the second memory cell, at a ninth timing,the gate electrode of the second transistor is supplied with athirteenth voltage, and at a tenth timing later than the ninth timing,the gate electrode of the second transistor is supplied with afourteenth voltage which is smaller than the thirteenth voltage, thethirteenth voltage is larger than the eleventh voltage.
 14. Thesemiconductor memory device according to claim 1, wherein when thecertain operation is a read operation, and in the case of the readoperation on the first memory cell, at an eighth timing, the first bitline is supplied with an eighth voltage, and at an eleventh timing laterthan the eighth timing, there is started a first sense operation, and inthe case of the read operation on the second memory cell, at a tenthtiming, the first bit line is supplied with a tenth voltage, and at atwelfth timing later than the tenth timing, there is started a secondsense operation, a time from the tenth timing to the twelfth timing islonger than a time from the eighth timing to the eleventh timing. 15.The semiconductor memory device according to claim 1, wherein when thecertain operation is a write operation, and the write operation includesa plurality of times of a program operation, and in the case of a firsttime of the program operation in the write operation on the first memorycell, at a thirteenth timing, the first conductive layer is suppliedwith a fifteenth voltage, and at a fourteenth timing later than thethirteenth timing, the first conductive layer is supplied with asixteenth voltage which is smaller than the fifteenth voltage, and inthe case of a first time of the program operation in the write operationon the second memory cell, at a fifteenth timing, the second conductivelayer and the third conductive layer are supplied with a seventeenthvoltage, and at a sixteenth timing later than the fifteenth timing, thesecond conductive layer and the third conductive layer are supplied withan eighteenth voltage which is smaller than the seventeenth voltage, atime from the fifteenth timing to the sixteenth timing is shorter than atime from the thirteenth timing to the fourteenth timing.
 16. Thesemiconductor memory device according to claim 1, wherein when thecertain operation is a write operation, and the write operation includesa plurality of times of a program operation, and in the case of a firsttime of the program operation in the write operation on the first memorycell, at a thirteenth timing, the first conductive layer is suppliedwith a fifteenth voltage, and at a fourteenth timing later than thethirteenth timing, the first conductive layer is supplied with asixteenth voltage which is smaller than the fifteenth voltage, and inthe case of a first time of the program operation in the write operationon the second memory cell, at a fifteenth timing, the second conductivelayer and the third conductive layer are supplied with a seventeenthvoltage, and at a sixteenth timing later than the fifteenth timing, thesecond conductive layer and the third conductive layer are supplied withan eighteenth voltage which is smaller than the seventeenth voltage, theseventeenth voltage is smaller than the fifteenth voltage.
 17. Asemiconductor memory device comprising: a substrate; a first conductivelayer which is separated from the substrate in a first directionintersecting a surface of the substrate and extends in a seconddirection intersecting the first direction; a second conductive layerwhich is separated from the substrate and the first conductive layer inthe first direction and extends in the second direction; a thirdconductive layer which is separated from the substrate and the firstconductive layer in the first direction, extends in the seconddirection, is aligned with the second conductive layer in the seconddirection, and is electrically connected to the second conductive layer;a first semiconductor layer which extends in the first direction andfaces the first conductive layer and the second conductive layer; asecond semiconductor layer which extends in the first direction andfaces the first conductive layer and the third conductive layer; a firstwiring which is electrically connected to the first conductive layer,the second conductive layer, and the third conductive layer; anoperation voltage output circuit which is electrically connected to thefirst wiring; and a variable resistance circuit which is provided in acurrent path between the first wiring and the operation voltage outputcircuit.
 18. A semiconductor memory device comprising: a substrate; afirst conductive layer which is separated from the substrate in a firstdirection intersecting a surface of the substrate and extends in asecond direction intersecting the first direction; a second conductivelayer which is separated from the substrate and the first conductivelayer in the first direction and extends in the second direction; athird conductive layer which is separated from the substrate and thefirst conductive layer in the first direction, extends in the seconddirection, is aligned with the second conductive layer in the seconddirection, and is electrically connected to the second conductive layer;a first semiconductor layer which extends in the first direction andfaces the first conductive layer and the second conductive layer; asecond semiconductor layer which extends in the first direction andfaces the first conductive layer and the third conductive layer; afourth conductive layer which is provided between the substrate and thefirst conductive layer, and is connected to one end of the firstsemiconductor layer and to one end of the second semiconductor layer; afirst wiring which is provided between the substrate and the fourthconductive layer, and is electrically connected to the second conductivelayer and the third conductive layer; a first contact which extends inthe first direction, whose one end in the first direction is closer tothe substrate than the fourth conductive layer is, whose other end inthe first direction is further from the substrate than the secondconductive layer is, and which is provided in a current path of thesecond conductive layer and the first wiring; and a second contact whichextends in the first direction, whose one end in the first direction iscloser to the substrate than the fourth conductive layer is, whose otherend in the first direction is further from the substrate than the thirdconductive layer is, and which is provided in a current path of thethird conductive layer and the first wiring.
 19. The semiconductormemory device according to claim 18, wherein the first wiring comprisesa plurality of first portions, and the plurality of first portionsextend in the second direction and are aligned in a third directionintersecting the first direction and the second direction, or extend inthe third direction and are aligned in the second direction.